AD1938 CODEC Full-Scale Input Voltage (Differential)

Hello Mahendrakumar,

Note that the specification is differential. 1.9Vrms. So this is 5.37Vp-p. But this is between two pins.

The pins sit at a common mode voltage of roughly 1.5V. So one pin needs to swing a total of 2.69 V for full scale input.

So this is 1.34V above and below the 1.5V. So the max will be 1.5V + 1.34V = 2.84V and 1.5V - 1.34V= 0.16V So this is the full swing of each pin. 

So since one pin will be full positive and the other pin full negative you get the full swing of 5.37V difference between the pins. Each pin individually is within the 3.3V and ground but the difference of the two will be greater. 

I know it is a bit tricky to see. Look at it on a scope and you can see this in action. 

You question about the power supplies. The AD1938 eval board was designed to have a lot more headroom and to be able to have more gain if desired. One was designed more for pro audio applications and the other for a lower cost solution suitable for most consumer applications. No huge secret here, just personal preference and applications needs.

Dave T

Hi Dave

I am replicating the AD1938 CODEC to my PCB. I am referring to the circuits from the UG-045 AD1938 eval board document. But I am not sure what these circuits are for. please help me understand what the circuit below does?

1) what this opamp circuit does before the audio input from the 3.5mm aux connector is fed to the CODEC ADC inputs?

2) why is the +12V and -12V power supply needed for the opamp(OP275)? can I just have a single 5V supply? If I just have a single positive supply what are the limitations I will have on the audio quality compared to  +12V to -12V opamp supply?

Appreciate your support!

Thanks

Santosh

Hello Santosh,

Question1) The input on the evaluation board is a single ended signal. The ADC input is differential. The circuit takes the single ended signal and makes it differential. The other thing it does is to change the reference of the signal from ground referenced to instead be referenced to 1.5V common mode voltage that is on the ADC input pins. This circuit actually gives you a choice. You can ground reference but then you require the large electrolytic cap to block the common mode voltage from being pulled down. If you do not want the cap then you need to use the CM voltage as a reference for the circuit. The CM voltage from the CM pin should always be buffered by a voltage follower if you decide to use it for the Vref. 

Question 2) The OP275 operates well with a +-12V supply. The specification for a full scale differential signal is 1.9Vrms between the two pins. 1.9Vrms = 5.37Vpp. Since this datasheet has been written there have been a number of OpAmps designed to operate on a single ended 5V supply. It really needs to be able to go rail to rail. Here is why:

The max input of a single pin of the ADC is around +2.84V on the positive swing and around +0.16V on the negative swing of an input signal. So if you can invert the signal to one Opamp and not the other, ( Which the circuit you included in your post does do ) then to reach full scale one OpAmp drives one pin up to +2.84V and the other OpAmp drives the other pin down to +0.16 and that gives you the 5.37V differential between the two pins. 

Therefore, the Opamps need to be able to swing between 0.16V and 2.84V when operated using a single 5V supply. ) 0.16V is very close to the negative rail of the Opamp, in this case that is ground. +2.84 is not all that close to the positive rail but not all Opamps designed to use single ended supplies can do this. I found that out once in a design I did. The output of the Opamp would not go over 2.5V. I pulled my hair out trying to see what I did wrong in the circuit until I reread the datasheet and noticed that the positive swing of the Opamp was Vcc-2.5V. So with a 5V supply the max was 2.5v!! 

So you can use a single 5V supply. You have to choose good Opamps that can go rail to rail and you have to reference the Opamps to either 2.5V or you can use the CM voltage of 1.5V.  Keep in mind that the ADC pins are riding up at the 1.5V CM voltage and you must not pull this up or down. 

The other factor is that some Opamps do not perform as well when they are close to the rails. So now the "sounds good" subjective factor comes into play. Most of the really good sounding Opamps operate on bi-polar supplies. But getting into that discussion is like opening up a Pandora's Box!

If you need help choosing an OpAmp then post a question on the linear amplifiers section of the forum. 

One other thought on the choice to use +-12V. For many pro-audio designs the signal levels can be as high as +21dBu. For that level +-12V is still not high enough. Usually pro circuits use +-18V or greater and the low ones use +-16V but those designs use transformers to get the +6dB more on outputs. So if you are interfacing with pro audio equipment you will need to amplify the DAC outputs and be able to take in a high level signal and attenuate it for the ADC inputs. Hence using a higher bi-polar power supply for the Opams. It is not so much for the codec but for the rest of the design. 

Dave T

Hi Dave 

Thanks for the detailed explanation. 

I understand the differential full-scale voltage of ADC input is 5.37Vpp but I am confused with the below paragraph

"The max input of a single pin of the ADC is around +2.84V on the positive swing and around +0.16V on the negative swing of an input signal. So if you can invert the signal to one Opamp and not the other, ( Which the circuit you included in your post does do ) then to reach full scale one OpAmp drives one pin-up to +2.84V, and the other OpAmp drives the other pin down to +0.16 and that gives you the 5.37V differential between the two pins"

1) What do you mean by inverting the signal to one opamp? 

2) one OpAmp drives one pin-up to +2.84V, and the other OpAmp drives the other pin down to +0.16 and that gives you the 5.37V differential between the two pins.....How is this? it is confusing to me? is my signal drawing in the image below correct?

Thanks

Santosh

Hello Santosh,

I drew some lines on your screenshot.

This is the signal path. The signal is inverted by U12-A and sent to the ADC,

Then this inverted signal is send through U12-B to be inverted again so it is back to not be inverted. That is sent to the other input of the ADC. So this is what I meant when I said one of the op amps input signal is being inverted. There are several ways to do this but the result will always be that one output is inverted and the other is not. 

So when one is going negative the other is going positive. 

The range of each ADC input is from +2.84V to +0.16V. The total range is the difference of these two numbers. So the voltage can swing a total of 2.68V. If one pin is fully positive and the other fully negative it is a differential swing of 5.36V. 

All I can say is that it works. Look at it on a scope and see the digital output. 

So I drew some more lines on your drawing as best as I could with a mouse.

Imagine the two lines I circled being drawn together as one line. Pull the graphics together. The overall swing will be 5.36V. 

I hope this helps. 

Dave T

Hello Santosh,

I drew some lines on your screenshot.

This is the signal path. The signal is inverted by U12-A and sent to the ADC,

Then this inverted signal is send through U12-B to be inverted again so it is back to not be inverted. That is sent to the other input of the ADC. So this is what I meant when I said one of the op amps input signal is being inverted. There are several ways to do this but the result will always be that one output is inverted and the other is not. 

So when one is going negative the other is going positive. 

The range of each ADC input is from +2.84V to +0.16V. The total range is the difference of these two numbers. So the voltage can swing a total of 2.68V. If one pin is fully positive and the other fully negative it is a differential swing of 5.36V. 

All I can say is that it works. Look at it on a scope and see the digital output. 

So I drew some more lines on your drawing as best as I could with a mouse.

Imagine the two lines I circled being drawn together as one line. Pull the graphics together. The overall swing will be 5.36V. 

I hope this helps. 

Dave T

Hi Dave

Thank you. I did a ltspice simulation and the confusion about signal waveform is clear now.

1) Should I have two GND planes Analog and Digital Ground for this CODEC on my PCB?

or a single GND plane is ok?

2) What should be the trace impedance for the ADC differential inputs? 50ohms single-ended or 100ohm differential?

Hi Dave 

any update on the above queries?

1) Should I have two GND planes Analog and Digital Ground for this CODEC on my PCB?

or a single GND plane ok?

2) What should be the trace impedance for the ADC differential inputs? 50ohms single-ended or 100ohm differential?

3) what to do with unused ADC inputs and DAC outputs? how to terminate them?

Thanks

Santosh

Hello Santosh,

One ground plane is best. Look at the ADAU1452 datasheet for how to layout bypass caps properly between the pins and the vias to the ground and power planes. 

For the AD1938 you should not put a ground plane on the top layer under the part that is connected to ground pins on the part. You can have a plane on the top layer but keep the pins from connecting to it. It is important for the ground pins to have only one trace go from the pin to the bypass CAP then to the ground plane on the top and vias to the ground plane. Keep all the bypass caps on the same side of the PCB that the codec is on. Keep the Loop Filter parts on the same side as the part and connections to the part short. 

Trace impedance for the ADC is not super important. It is good to make them the same. 75 or 50 ohms seems like a good number. Like I said, we do not specify anything specific. 

Unused ADCs, You should either tie them to the CM pin or you can tie them to ground through a cap. A 1uf to 10uf would be fine. Most of the time people will tie them to the CM pin for cost reasons. 

Unused DACs. These can be left floating with no connection. If you need to terminate all pins then use a 10K to ground. 

Dave T

Hi Dave

We need clarification on AD1938 MCLK Clock scheme.

Path 1: Host processor will feed the MCLK to CODEC.

Path 2: 12.288MHZ Oscillator will feed MCLK to Host processor and CODEC.

Please verify the MCLK Clock scheme is correct. Also clarify the below queries.

Queries:

1. We are implementing two clock paths as shown in the image on our board (TDM implementation) are these connections Path1 and Path2 valid?
2. What is the purpose and use of MCLKO pin ?
3. Can we make the MCLKO pin as “NO CONNECT” When the clock feed from path 1 or path 2?

Regards

R.Mahendra kumar

Hello R. Mahendra Kumar,

To get the best performance you need to use a low jitter clock. It is often not the best to get it from a host processor if it can be avoided. So I would opt for path 2 for sure. 

The MCLKO pin is actually a multi-use pin. If you use a crystal then you will need to set this pin to the crystal oscillator output function to allow a crystal to oscillate. 

If you use a clock oscillator module, or some other clock source, then you can program this to be a clock output that is after the internal PLL. This allows you to use the PLL to provide a cleaner clock to the rest of the design. 

If you are not going to use it for either use then you can shut it off. So yes, do not connect anything to the pin and shut it off in the register settings. 

You have not discussed the frame clock (LRCLK) and bit clocks. I recommend you use the ADC LRCLK and BCLK outputs to drive the host processor. This way you use the internal PLL to run the ADC and then slave the host off of that. The ADC is the most susceptible to jitter so this will produce the bast performance. 

When you start the PCB layout check the forum. I have commented on the layout for these parts several times and there are some important things to do to prevent problems. 

Dave T

Hi Dave

• I have attached the signal path for LRCLK and BCLK also. Please verify this and provide your suggestions.
• Also please share the links for suggested layout guidelines for AD1938.

Regards

R.Mahendra kumar

Hi Dave

Is there any update on above Query?

Regards

R.Mahendra kumar

Hello R.Mahendra, 

This is what I suggest.

What sample rate do you intend to use?

What TDM format? ( how many channels) It looks like you plan to use TDM8?

Look at the PCB design considerations section of the ADAU1452 datasheet. The newest revision that I did back in 2018? 

Then the other detail is not to connect the pad under the device to anything except a bunch of vias to the ground plane. Do NOT tie it to any of the ground pins of the part. Let those go past a capacitor then to ground on their own vias. You will have to keep the ground plane on the top from filling into the pain and the EP on the bottom of the part. Do not let them connect. 

ALL of the decoupling caps must be on the top of the PCB and connected like the ADAU1452 datasheet shows. . 

Dave T

Hi Dave

We are using 8k, 16k, 32k, 48k, 96khz sampling rates and TDM8 format.

Also, we are planning to use AD1938 CODEC to test our Host processor (DUT) TDM interface.

From the above diagram, please confirm the below points.

1. To connect CODEC mclko to rx mck is to ensure that the interfaces are synchronous to each other, or is there some other explanation?
2. In this, what happens to the txmck from host?
   For synchronous behavior, we think that the tx mck also has to be provided from the mcko, just like rx mck.
3. Rx_fsync – Alrclk, Rx_sck – Abclk, connections would be bidirectional, as per master / slave configuration, right?

Regards

R.Mahendra kumar

Hello R.Mahendra kumar,

Mahendrakumar said:

To connect CODEC mclko to rx mck is to ensure that the interfaces are synchronous to each other, or is there some other explanation?

Yes, to make them synchronous. 

Mahendrakumar said:

In this, what happens to the txmck from host?

You do not use it. No, you do not need to use the txMCK unless that processor is not capable of using an external clock. It seems to be it can but I do not know that part. I am just advising you of the best way to do clocking with the least amount of jitter. 

Mahendrakumar said:

Rx_fsync – Alrclk, Rx_sck – Abclk, connections would be bidirectional, as per master / slave configuration, right?

The pins on the codec are bi-directional but the directions I showed should be followed. This will give you the best timing margin for the data transmission and to be able to run at the higher sample rates. You are asking me what is the best way and this is the best way. 

Dave T