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Schematic review request for ADAU1761BCPZ Audio-Codec

Thread Summary

The user requested a schematic review for the ADAU1761BCPZ audio codec. The final answer confirmed that input pins LINP and RINP should be tied to the CM voltage, not grounded, and that the 1K ohm resistors on LOUTN and ROUTN should not be populated. The user also clarified that the input signal is connected to two different inputs with 0-ohm resistors for flexibility, and that the pin numbers were corrected. A subsequent issue with no output on the line outputs when using a 4KHz square wave input was noted, with the only difference being the MCLK source (oscillator vs. FPGA).
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Hi,

We're using ADAU1761BCPZ in our project. 

kindly request you to go through the schematic and review it.

Attached below schematic as pdf.

PDF

  • Hello muthukumar,

    The 1K ohm resistors to ground on the LOUTN and ROUTN pins need to be removed. There is no need for them to be there and it will only pull down the CM voltage that is sitting on the pin. Figure 48 in the datasheet shows the configuration of the outputs. 

    The two 10K resistors to ground on the outputs pins should be a higher value like 49K. The output can drive a 10K load but why put that much load on the output when the only reason those resistors are there is to prevent the leakage from the cap to rise up and create a pop when something is plugged in. 

    L1 and C421 are not needed unless this is going into a GSM phone. That is what the filter was designed for. 

    You never want to ground the LINP or RINP pins. Those pins are up at a CM voltage.

    Why do you have the input signal going to two different inputs? This will only cause more of a load for the circuit driving these inputs. If you want a choice then place some 0-ohm resistors in series so you can stuff one and not the other. 

    One last but super important thing. Your pin numbers are all wrong. I think you might end up with some of the magic smoke escaping from the part if you use these pin numbers and power up the part. 

    Dave T

  • "You never want to ground the LINP or RINP pins. Those pins are up at a CM voltage": Yes, It'll be connected to Analog Bias

    " Why do you have the input signal going to two different inputs? This will only cause more of a load for the circuit driving these inputs. If you want a choice then place some 0-ohm resistors in series so you can stuff one and not the other." : Please clarify this.

    Attached modified schematic below

    PDF

  • Hello muthukumar,

    This is your answer:

    "You never want to ground the LINP or RINP pins. Those pins are up at a CM voltage": Yes, It'll be connected to Analog Bias

    I do not see it tied to analog bias. It is tied to ground through a 1K resistor. You do not have to terminate these and I would not tie it to Analog Bias. This will cause the signal to be driving Analog Bias. Just leave it unterminated. 

    Next:

    " Why do you have the input signal going to two different inputs? This will only cause more of a load for the circuit driving these inputs. If you want a choice then place some 0-ohm resistors in series so you can stuff one and not the other." : Please clarify this.

    You have made some changes. It is difficult for me to read the net names.

    But I still see net name issues. These seem to be the same names:

    Dave T

  • You have made some changes. It is difficult for me to read the net names.

    Those two input net names are different.

    I do not see it tied to analog bias. It is tied to ground through a 1K resistor

    LINP and RINP are tied to analog bias. R284, R288 are by default not populated.

    LOUTN and ROUTN are left open. By-default R285 and R289 are not populated.

  • Hello 

    There was some confusion in that I was talking about the output pins should not be tied to the CM voltage but you were talking about the line in. I did miss-type it as well. So now we are clear. It is fine to tie the input pins to the CM voltage and I see you are not going to stuff the resistors on the output. 

    So you are good. I am just wanting to try to catch any errors. 

    Thanks,

    Dave T

  • Hi,

    We came across a problem where we do not see any output on the Line outputs, when the input to Line LINN and RINN is 4KHz square wave signal.

    We have tried the same configuration with ZED board, we do see the outputs on Line outputs.

    The only difference between ZED board and our board is MCLK. In ZED board MCLK is through FPGA and in this board is through oscillator.

    MCLK-12.288MHz,BCLK- 3.1MHz, LRCLK-48KHz.

  • Hi Team,

    In one of my new application I want to use One Mono out differential and one stereo output differential lines from the ADAU1761 IC.

    I will use LOUT P and LOUT N or ROUT_P and ROUT_N for mono differential, can I convert the LHP and RHP to an differential Lines and connect to an headphone as differential lines. If yes, please specify the way to do it.

    Regards,

    Muthu Kumar R

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