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ADAU1787 anti-aliasing and simultaneous multiple sample rates


We wish to use the ADAU1787 for ADC functions only.

I am not clear from reading the datasheet and playing with SigmaStudio how exactly anti-alisaing filters are implemented in the ADAU1787.

For example, if running ADC01 at FS768K, does the part internally oversample and then apply a LPF (with cutoff < 0.5 Fs) to ensure there is no aliasing in the output data? Or is an external anti-aliasing filter required in hardware to band-limit the incoming ADC signals to < 384KHz?

Similarly, if we wish to sample at FS48K with no aliasing, is it enough to select FS48K in eg ADC01_FS with no external hardware filters or band limiting? I assume that each ADC is oversampled and followed by a decimation filter which applies an LPF and then downsampling to the final sample rate, even when that rate is FS768K?

Oversampling is never mentioned explicitly in the datasheet, nor is aliasing or anti-aliasing. 

My second question is, is it possible to run ADC01 at 48KSPS and ADC23 at 768KSPS, and then output ADC0 stream (48KSPS * 16bit) and ADC2 stream (768KSPS * 16bit) simultaneously on the same serial output port? 

Or, is it possible to output stereo 768KSPS, but band-limit one of the channels to <=24KHz, so that on the receiving end of the I2S link we can simply discard samples to downsample that channel to 48KSPS, while keeping the other channel at 768KSPS?

I am unclear on the operation of the "decimator" and "interpolator" blocks shown in "Figure 53. Input and Output Signal Routing". Are the decimator blocks shown here completely independent of the decimation block which is implied to be part of the ADC blocks in Figure 1? Does the decimator block in Figure 53 apply an LPF and then downsample, or merely apply the LPF, or only perform downsampling without any bandlimiting, meaning aliasing could occur?

For our use case of simultaneously sampling at FS48K and FS768K, would it be possible to run eg ADC0 at FS48K, route it to interpolator to increase to FS768K, and then route this out of eg left stereo channel of SPT0 while outputting ADC2 running at FS768K directly out right stero channel of STP0?


- Wayne