ADAU1452 & 192kHz TDM output to AD1938

Hello, I'm using an ADAU1452 board connected to an AD1938 codec board (commercial board, I did not design it). The ADAU1452 provides a master clock to the AD1938 starting from a 12.288MHz crystal, The AD1938 is configured from a pre-programmed 8 bit processor with data I cannot change. I captured the data on the bus with a logic analyzer, and when setting the jumpers for 192kHz rates, the values are as follows

Reg Value Binary Name Settings
00 BE 10111110 PLL0 PLL normal, Input 768, MCLK XO Off, PLL input DLRCLK, ADC and DAC active
01 F8 11111000 PLL1  DAC source PLL, ADC source PLL, on-chip voltage off, PLL locked, 
02 44 01000100 DAC Ctl0 Power on, 192kHz rate, SDATA delay=1, serial format=TDM
03 0E 00001110 DAC Ctl1 Latch in mid cycle, BCLK per frame=512 (16 channels), LRCLK left=high, LRCLK slave, BCLK=slave, BCLK source=DBCLK, BCLK polarity normal
04 C0 11000000 DAC Ctl2 Unmute, de-emphasis flat, 24 bit word width, output polarity noninverted
05 00 00000000 DAC Ch Mute All unmuted
06 00 00000000 DAC L1 Vol No attenuation
07 00 00000000 DAC R1 Vol No attenuation
08 00 00000000 DAC L2 Vol No attenuation
09 00 00000000 DAC R2 Vol No attenuation
0A 00 00000000 DAC L3 Vol No attenuation
0B 00 00000000 DAC R3 Vol No attenuation
0C 00 00000000 DAC L4 Vol No attenuation
0D 00 00000000 DAC R4 Vol No attenuation
0E 80 10000000 ADC Ctl0 Power on, high pass off, all unmuted, output rate 192kHz
0F A0 10100000 ADC Ctl1 24 bit word width, SDATA delay=1, serial format=TDM, BCLK latch in mid cycle
10 36 00110110 ADC Ctl2 LRCLK=50/50, BCLK out on rising edge, LRCLK left=high, LRCLK slave, 512 BCLK per frame, BCLK slave, BCLK source=ABCLK

I successfully created a project in SigmaStudio for the ADAU1452 with 96kHz. The 4 input channels are sent as 4 channel, 32 bits per channel on serial port SDATA_IN0, and recognized properly. And the 8 output channels are sent as 8 channels 32 bits on SDATA_OUT0, also working properly and each channel is correctly mapped to the right DAC output

I then tried to create a similar project, with a 192kHz rate. The input part works just fine, but for some reason the output part is sending the frames to the wrong DAC (i.e. the first fra,e which should be mapped to channel 0, is instead mapped to channel 2. Channel 0 receives frame 6 and channel 1 frame 7 from the previous packet. I did also use a logic analyzer, and I see the same thing on the logic analyzer, with the packet shifted.

I'm pretty sure that I messed up the clocking part of my project. And I'm not entirely sure if the 96kHz portion is correct either, even if that seems to work and the signal frequencies look good also on an oscilloscope/logic analyzer.

I'd rather not upload my project, because I'm afraid I would simply confuse things for everyone. Would it be possible to either provide the full description of the clock_control and serial_ports sceens, or even better upload here a dspproj file for a 192kHz ADAU1452 core, reading a 4 channel ADC data stream from serial port in 0 and outputting the same data mapped as 8 channels TDM on serial port out 0, both in and out streams at 192kHz (no ASRC needed)? I'm sorry to ask, but at this point I'm lost and outside of randomly trying all possible clocking combinations, I'm not sure what else I can do. The ADAU1452 has such a flexible clocking framework that I fear is beating my ability to figure it out :). Thanks in advance for any help

As feedback, it would be good if a future version of SigmaStudio included a sort of wizard, that guides the user to create a project from scratch by asking a few questions (core frequency, types of input and output, etc) and based on those automatically create the dspproj with the pre-set clocking, power and serial ports settings (to be further modified as needed by the user). Creating a scaffolding with a wizard is a pretty common option for development tools, and in my experience greatly helps bootstrap development

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  • +1
    •  Analog Employees 
    on Jun 18, 2021 2:34 AM

    Hello robca,

    There are some problems with the setup that you cannot change. 

    First, the part cannot handle TDM 16 at sample rates above 48kHz. The bitclock rate cannot be greater than ~ 24MHz. ( the spec is a little higher than that but TDM 4 at 192kHz is a 24.576MHz bit clock which is the max for the standard rates) 

    Then there is the issue of timing margins with a 24MHz bit clock. Running the ADC in slave mode is not the best if you are trying to run at 192kHz. For the DAC slave mode is best but you will need to increase the drive strength on the LRCLK, BIt CLock and SDATA out of the DSP serial ports. This will help with the timing margins. 

    Then the master clock setup is a bit different. The PLL input is setup to take a LRCLK as input not the MCLKIN pin. So it does not matter what is on the MCLK pin, it is taking the DSDATA pin. It is setup for 192kHz so if you put in a lower rate the internal clocks will be too slow. So the entire setup is just wrong. My next question would be what are the filter components of the PLL Loop filter? The values need to be different if it is an LRCLK or a MCLK input. So what is stuffed on the board?

    If it were not for the PLL issue, you could run the part by sending it lower frequency bit clock and some things will work. 

    The ADC will work fine and you found that. It is setup for TDM16 but it is just s shift register so if you shift out the ADC data and then the end of the frame comes up it just resets and starts over. So you do not need to shift out 16 channels. 

    For the DAC it is a little different. In the TDM-Daisy Chain mode that the part is set in causes an issue. Look at Figure 18 in the datasheet. In this mode the first 8 channels are meant to just shift back out to go to the next DAC and the last 8 channels of the 16 are to be used for the local DACs. Well, if you try the trick of sending a lower frequency bit clock the data will come in and go out and nothing will get to the DACs. 

    So I think you are stuck and need to find a way to change the microcontroller code. Another option that might be possible is to disconnect the controller from the comms port of the codec and connect the master port of the DSP to the codec. Then you can setup the DSP to program the codec. Is there a selfboot EEPROM for the DSP? What type is it, SPI or I2C?

    Dave T

  • First of all, thanks for the incredibly detailed answer. I have to say I'm always impressed by the quality of the answers on this forum.

    I'm using a cheap Chinese board, and obviously using the device out of specs is not a concern for the designer. I just checked, and the bclk0 signal is ~49MHz,Mclk is also ~49MHz.  Lrclk is 192kHz. Surprisingly, the AD1938 seems to still work at those rates, mostly. I'm also including a screen capture with PulseView and a DsLogic analyzer running at 400MHz acquisition rate, to show the signals from the ADAU1452 to the AD1938.

    I will use the board for now at lower rates, until I have time to hack into it and use my own microprocessor to set up the proper values. The ADAU1452 board actually already has an STM32F1 onboard, connected to the SPI of he ADAU1452. I need to remove the low end processor from the separate codec board and connect the right pins to a secondary SPI port of the STM32, and I can control both from the same processor. At that time I'll also revisit the PLL loop filter components, thanks for the heads up on that.It's a cheap board and I'm using it to learn the basic concepts before buying something better (or building my own). Unfortunately it's very hard these days to build a prototype board, with multiple chips being unavailable for long periods of time. So the cheap board is still useful for the purpose I got it for.

    Thanks again for helping me understand what was happening

Reply
  • First of all, thanks for the incredibly detailed answer. I have to say I'm always impressed by the quality of the answers on this forum.

    I'm using a cheap Chinese board, and obviously using the device out of specs is not a concern for the designer. I just checked, and the bclk0 signal is ~49MHz,Mclk is also ~49MHz.  Lrclk is 192kHz. Surprisingly, the AD1938 seems to still work at those rates, mostly. I'm also including a screen capture with PulseView and a DsLogic analyzer running at 400MHz acquisition rate, to show the signals from the ADAU1452 to the AD1938.

    I will use the board for now at lower rates, until I have time to hack into it and use my own microprocessor to set up the proper values. The ADAU1452 board actually already has an STM32F1 onboard, connected to the SPI of he ADAU1452. I need to remove the low end processor from the separate codec board and connect the right pins to a secondary SPI port of the STM32, and I can control both from the same processor. At that time I'll also revisit the PLL loop filter components, thanks for the heads up on that.It's a cheap board and I'm using it to learn the basic concepts before buying something better (or building my own). Unfortunately it's very hard these days to build a prototype board, with multiple chips being unavailable for long periods of time. So the cheap board is still useful for the purpose I got it for.

    Thanks again for helping me understand what was happening

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