Hi

I've checked past question below but it's not clear for me to understand how to treat LR_POL bit in case ADAU197x is slave, TDM pulse mode.

Figure 28 is an example of TDM pulse mode with LRCLK_MODE=1(high first)

LR_POL needs to set up to fit SDATA_FMT from my experiment with Eval board, but I'd like to understand the log.

LR_POL=0 for I2S Data Delayed from Edge of LRCLK by 1 BCLK?

LR_POL=1 for Left Justified?

Regards,

Tomoto

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• Hello Tomoto,

The LR_POL is not shown in any of the diagrams. It only swaps the polarity of the LRCLK output and what it is expecting when it is a clock slave.

So in the 50/50 LR clock mode for I2S signals it will change the left channel from being sent out when the LRCLK is low to be high instead. So the start of the frame will be when the LRCLK is high rather than low.

So when it is zero the left channel is low for the left channel and high for the right.

In TDM mode where the LRCLK mode is often a pulse format. In that format the LRCLK usually goes high for one bit clock period. This will be for the LR_POL = 0.

For LR_POL = 1 is the opposite where the one bit clock wide pulse would be negative going.

Hope this helps.

Dave T

• Hello Tomoto,

The LR_POL is not shown in any of the diagrams. It only swaps the polarity of the LRCLK output and what it is expecting when it is a clock slave.

So in the 50/50 LR clock mode for I2S signals it will change the left channel from being sent out when the LRCLK is low to be high instead. So the start of the frame will be when the LRCLK is high rather than low.

So when it is zero the left channel is low for the left channel and high for the right.

In TDM mode where the LRCLK mode is often a pulse format. In that format the LRCLK usually goes high for one bit clock period. This will be for the LR_POL = 0.

For LR_POL = 1 is the opposite where the one bit clock wide pulse would be negative going.

Hope this helps.

Dave T

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