ADAU197x LR_POL setting

Hi

I've checked past question below but it's not clear for me to understand how to treat LR_POL bit in case ADAU197x is slave, TDM pulse mode. 

https://ez.analog.com/audio/f/q-a/3700/about-a-register-bit-lr_por-on-adau1977-adc/1588

Figure 28 is an example of TDM pulse mode with LRCLK_MODE=1(high first)

LR_POL needs to set up to fit SDATA_FMT from my experiment with Eval board, but I'd like to understand the log.

LR_POL=0 for I2S Data Delayed from Edge of LRCLK by 1 BCLK?

LR_POL=1 for Left Justified?                                                                

Regards,

Tomoto

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