ADAU1328 "TDM (8-Channel I2S Mode) question

I'm trying to get the ADAU1328 working in slave mode with 8 output channels and 4 input channels, and according to my oscilloscope, I am duplicating the timing shown in Figures 12 and 13 in the ADAU1328 datasheet. At the moment, I am just focusing on the 8 DAC channels.

While Figure 13 refers to this as "TDM (8-Channel I2S Mode)", I find no reference to that mode in the Serial Format Field in the DAC Control 0 register. The way I got anything at all to work was to select "Stereo (normal)" and set the "BCLKs per frame" field in the DAC Control 1 register to "256 (8 channels)", but this doesn't seem right to me. With these settings, channel 0 appears to work, but none of the others do.

In order to reproduce Figure 13 timing, I had to lengthen LRCLK from a pulse at the beginning of the frame (low during slot 1 only, normally called Frame Sync) to a 50% duty cycle square wave (low during slots 1 - 4, high for slots 5 -8). Is this correct? Is there a TDM8 mode which uses a more typical FS? Again, that doesn't appear to be a choice in the DAC Control registers.

So my main question:

1) In order to have just 8 output channels, is Figure 13 the correct timing diagram, and if so, what are the appropriate control register settings? If not, which is the correct timing diagram?



Added the fact that the ADAU1328 is in slave mode
[edited by: robertsonics at 1:24 AM (GMT -4) on 27 May 2021]
  • Also, I thought I'd share a screenshot of the MCLK trace route from the S70 to the Codec, as you said earlier this could be playing into this. Thanks for taking a look!

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    •  Analog Employees 
    on Jun 1, 2021 6:49 PM in reply to rockonaudio

    Hello Pete,

    Thanks for the info, sorry for the short delay in my response.

    The LRCLK values will make it optimum for using it with an LRCLK as a clock source. I find that it does not prevent the PLL from locking but it might take longer or not lock at temperature extremes. So this might be part of the problem but not the entire issue. So for sure replace the filter with the MCLK values as a good start. 

    Yes, touching it will filter the noise and change a bunch so I think you found the solution,... you have to be shipped with the product and stand there touching the loop filter! LOL 

    The test does show that we are closing in on the issue that it is a PLL locking issue. 

    OK, Layout... Hard to explain this in a post without making it a short novel. Download the ADAU1452 datasheet and look at the example PCB layout on page 193. This will show how bypass caps should be connected to the power planes. 

    The other detail is that you should not tie to a plane that is under the part. 

    Here is an example:

    I drew in red "x" where the traces should not be going anywhere. I drew a couple of red circles to show where you should place a via and connect to ground and power planes. You should make a small VCCA power plane under this section of the part. This will make the bypass caps much more effective. 

    On the corners you need to place the bypass caps between the power and ground pins and again, make the current path from the pin to HAVE to go past the bypass caps on the way to the power and ground planes. Here is a rough sketch: 

    I see you have two power planes. Analog and Digital. We always use only one ground plane for both the DGND and AGND ground pins. Inside the part they are connected. I understand you most likely have different grounds in your system. Connecting the bypass caps in the manner I am describing will help and getting the correct loop filter components will help a lot and you might not need to use one ground. 

    One funny little thing, my first look at your screenshot made it look like the LF pin was tied to ground and all the ADC input pins! But your software is showing something in yellow/green that is clearly not copper! I saw this elsewhere in the screenshot where it was clear that the part would not be working if this was truly connected! 

    Do don't tie the ground pins to any of the top ground fill unless it is going past a bypass cap. 

    Dave T

  • 0
    •  Analog Employees 
    on Jun 1, 2021 7:02 PM in reply to rockonaudio

    Hello Pete,

    I forgot to comment about the MCLK trace. 

    You probably should have a damping resistor in series with the MCLK signal. The line is close to the length where you should have one. The test point will cause a reflection but  as long as the drive strength is not too high it will probably not be an issue. To properly design the transmission line you should use a signal integrity simulation software to help determine the value of the resistor. 22 -33 ohms is a good ballpark but just a guess. I am not expecting this to be the issue. But, I am wondering if you have a four layer board? You need to have at least four layers with the power and ground planes on internal layers. 

    Dave T

  • Hey Dave T,

    Thanks for all your feedback. Good news, we swapped out the PLL filter values and it seems to have cleared up the issue!

    Nevertheless, I have also implemented your layout feedback. However, we are trying to stay at 2-layers, and so I do not have a VCC plane. In stead, I have it routed with a thicker trace on the bottom copper (and still trying to maintain good bottom copper AGND plane. I have also removed the analog GND from the top layer (underneath the IC) - and now am making all of the AGND connections with vias to the bottom copper AGND plane.

    Also note, sorry about the confusion about  the yellow layer in my previous images. That was the "tDocu" layer in Eagle, and it is not copper, and intended to help the designer keep track of actual leg length and part sizes.

    Here are my new cap placements and routes to vias.

    And here is a wider shot with the VCC net highlighted:

    And here is a closer shot of the PLL filter loop (I was able to tighten that up a bit):

    I wasn't sure how to handle this additional AGND pin at pin 32, so I just grounded to AGND with a via nearby. Is this okay, or should it be routed to the GND via next to the nearby bypass caps?

    Thanks again and I look forward to your response!

    Cheers,

    Pete

  • 0
    •  Analog Employees 
    on Jun 15, 2021 7:14 PM in reply to rockonaudio

    Hello Pete,

    This is better but still you should have four layers. 

    Glad it is working now. 

    Dave T