ADAU1328 "TDM (8-Channel I2S Mode) question

Hello robertsonics,

This part was developed when TDM was still relatively new so the names and descriptions of some of the registers can be a bit confusing. 

I am glad to hear that you are using a scope to look at this. At some point it would be good to post some screenshots if you have more questions. 

Set it to TDM Mode. 

DAC Control 0 register, bits 7:6 and set it to "01"

Set the SDATA delay to the setting you desire. Usually it is set to the default which is setting zero for a delay of one bit clock period. 

On DAC Control 1 register:

For a TDM format of 32 bits per channel and 8 channels you have to tell the part that there will be 256 bitclock cycles to latch in 256 bits of data per frame. 

Now if you are sending a pulse that goes low for the start of the frame then I am fairly certain that you have to invert the LRCLK polarity. This may have been part of the issue.   

Let me discuss the LRCLK ( Frame Clock ) 

This part has a few quirks. For some reason the designers did not give a choice for LRCLK format when in master mode. If you are set to stereo it will produce a 50/50 duty cycle and in TDM it will produce a pulse. No choice. 

For slave mode it does not matter too much. The part only looks for the start of the frame and for some settings it does not pay attention to the transition in the middle of the frame. You should be able to get it to work with the 50/50 duty cycle. The LRCLK polarity will only swap channels 1-4 with 5-8. You should be able to get this to work with the 50/50 duty cycle. Then switch back to the pulse mode and try changing the LRCLK polarity. 

What is the frequency of the master clock?

Is the DAC in slave mode? ( it seems to be )

Are the clocks ( LRCLK and BCLK ) derived from the master clock? Are they synchronous is the real question. If they are not then the DAC will mute.

One other thing... What are you doing with the PLL? Are you using it for both the DAC and ADC? There is a strange little bug in this part that if you are directly clocking the DAC and using the PLL for the ADC and the PLL is not locked, it will mute the DACs. 

One other little thing is that you can search the forum for help with the AD1938. This part is pretty much the same part so any advice for settings on the 1938 will apply to this part minus the additional ADCs of course. 

Dave T

Thank you! It's very reassuring to know that such knowledgeable help is available. This particular datasheet is not as clear or precise as it could be, I'm afraid.

Your answers regarding TDM make sense. The wording in the datasheets for bits 7:6 as "TDM (daisy chain)" confused me since I'm not doing daisy chain. Regardless, setting them to this mode and inverting LRCLK polarity seems to have worked. I'm getting multiple channels output now.

Your "One other little thing..." comment leads me to a second issue that I was saving until the first was resolved. Due to my confusion about the clocks section in the datasheet, I am currently using the PLL for both the DAC and ADC, referencing it to the 11.2896MHz MCLK input. During initialization, I make sure the PLL indicates as "locked" before proceding.

However, as you can see from the scope capture image, the DAC output is occasionally going to 0. The top yellow trace is the TDM data input, and the bottom purple trace is the analog output of DAC channel 1. The signal is a 440Hz sine wave. You can see the during the time that the DAC output goes to 0, the TDM input is uninterrupted, indicating that the DAC is indeed being muted. I'm guessing it has to do with the PLL.

I wasn't sure from the datasheet whether the DAC and ADC will run directly from the external MLCK input. Can I power down the PLL and set the DAC and ADC source select to "MCLK"? The bit 7 field of PLL and Clock Control 0 register confused me: What is the "Internal MCLK" and why does it say "ADC and DAC Idle" if it's disabled?

I guess my question is this: If it's possible to not use the PLL and use the MCLK input directly, what are the correct setting for the PLL and Clock Control 0 and 1 registers.

Thanks again for your help

Thank you! It's very reassuring to know that such knowledgeable help is available. This particular datasheet is not as clear or precise as it could be, I'm afraid.

Your answers regarding TDM make sense. The wording in the datasheets for bits 7:6 as "TDM (daisy chain)" confused me since I'm not doing daisy chain. Regardless, setting them to this mode and inverting LRCLK polarity seems to have worked. I'm getting multiple channels output now.

Your "One other little thing..." comment leads me to a second issue that I was saving until the first was resolved. Due to my confusion about the clocks section in the datasheet, I am currently using the PLL for both the DAC and ADC, referencing it to the 11.2896MHz MCLK input. During initialization, I make sure the PLL indicates as "locked" before proceding.

However, as you can see from the scope capture image, the DAC output is occasionally going to 0. The top yellow trace is the TDM data input, and the bottom purple trace is the analog output of DAC channel 1. The signal is a 440Hz sine wave. You can see the during the time that the DAC output goes to 0, the TDM input is uninterrupted, indicating that the DAC is indeed being muted. I'm guessing it has to do with the PLL.

I wasn't sure from the datasheet whether the DAC and ADC will run directly from the external MLCK input. Can I power down the PLL and set the DAC and ADC source select to "MCLK"? The bit 7 field of PLL and Clock Control 0 register confused me: What is the "Internal MCLK" and why does it say "ADC and DAC Idle" if it's disabled?

I guess my question is this: If it's possible to not use the PLL and use the MCLK input directly, what are the correct setting for the PLL and Clock Control 0 and 1 registers.

Thanks again for your help