I'm trying to get the ADAU1328 working in slave mode with 8 output channels and 4 input channels, and according to my oscilloscope, I am duplicating the timing shown in Figures 12 and 13 in the ADAU1328 datasheet. At the moment, I am just focusing on the 8 DAC channels.
While Figure 13 refers to this as "TDM (8-Channel I2S Mode)", I find no reference to that mode in the Serial Format Field in the DAC Control 0 register. The way I got anything at all to work was to select "Stereo (normal)" and set the "BCLKs per frame" field in the DAC Control 1 register to "256 (8 channels)", but this doesn't seem right to me. With these settings, channel 0 appears to work, but none of the others do.
In order to reproduce Figure 13 timing, I had to lengthen LRCLK from a pulse at the beginning of the frame (low during slot 1 only, normally called Frame Sync) to a 50% duty cycle square wave (low during slots 1 - 4, high for slots 5 -8). Is this correct? Is there a TDM8 mode which uses a more typical FS? Again, that doesn't appear to be a choice in the DAC Control registers.
So my main question:
1) In order to have just 8 output channels, is Figure 13 the correct timing diagram, and if so, what are the appropriate control register settings? If not, which is the correct timing diagram?
Added the fact that the ADAU1328 is in slave mode
[edited by: robertsonics at 1:24 AM (GMT -4) on 27 May 2021]