ADAU1761 sigma Studio PLL compiling problem

For our new design we use the ADAU1761 codec. When I create the project and compiling it, the PLL settings switch from PLL enable to PLL disable. (see attached images)

We are using this codec for many similar projects with no problems. But even I am loading old and working project to the new board, I have this behavior. What can cause that?

Thank you.

Mark Naiditch

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    •  Analog Employees 
    on Aug 17, 2021 9:28 PM

    Hello naimark,

    Sorry for the delay in responding.

    Usually this happens when there is no communication between SigmaStudio and the DSP. SigmaStudio reads back the PLL and clock settings after setting up the DSP and if it does not get an answer it replaces the values with zeros. This is what I usually find when this happens. 

    You will also find that the core is stopped. 

    Dave T

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  • 0
    •  Analog Employees 
    on Aug 17, 2021 9:28 PM

    Hello naimark,

    Sorry for the delay in responding.

    Usually this happens when there is no communication between SigmaStudio and the DSP. SigmaStudio reads back the PLL and clock settings after setting up the DSP and if it does not get an answer it replaces the values with zeros. This is what I usually find when this happens. 

    You will also find that the core is stopped. 

    Dave T

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