[SOLVED] SSM2603 right output offset issue

[SOLUTION]

Sooooo, I finally found the problem after month of struggle!

So it turned out that the problem came from the SSM, not from my code...

First, I finally identify that the problem only occur when I was configuring the SSM the first time after booting.

If I reconfigured it later, without powering down to the board (and the codec), it worked every time.

I validated this theory by calling the configuration function twice in a row: no more problems.

So after some empirical tests, I finally found the fault register: R06 (power management)

Unlike what is written on the datasheet:

"Enable all of the necessary power management bits of
Register R6 with the exception of the out bit (Bit D4)."

You have to leave the default values! (everything power down except OSC and CLKOUT bits).

Here is my code:

I haven't had any problems since. Tested on a dozen zybo (Z10 and Z20).

I don't know if I'm the only one who had this problem.

I hope it can help someone else and save you wasting as much time as me on this codec...

[SOLUTION]

Sooooo, I finally found the problem after month of struggle!

So it turned out that the problem came from the SSM, not from my code...

First, I finally identify that the problem only occur when I was configuring the SSM the first time after booting.

If I reconfigured it later, without powering down to the board (and the codec), it worked every time.

I validated this theory by calling the configuration function twice in a row: no more problems.

So after some empirical tests, I finally found the fault register: R06 (power management)

Unlike what is written on the datasheet:

"Enable all of the necessary power management bits of
Register R6 with the exception of the out bit (Bit D4)."

You have to leave the default values! (everything power down except OSC and CLKOUT bits).

Here is my code:

I haven't had any problems since. Tested on a dozen zybo (Z10 and Z20).

I don't know if I'm the only one who had this problem.

I hope it can help someone else and save you wasting as much time as me on this codec...

Hi MaxPof

Thanks for your solution !!
You are absolute correct! There is an error in the manual for SSM2603, about how to initiate the registers,
or a very very bad description!

I have been working with this problem on/off for about 3/4 year !
Sometimes the codec start up fine and other times not - where you get this "broken" sinus signal - and VMID ends up at 3.3 V not 1.65 Volt as excepted.

I follow your solution (almost) setting all power pin in reg. 6 to 1 - also setting Hole chip to "power down", (which is rather unlogic ally).
Making my settings to other registers,  - and then after the a times delay at about 100 msec power up the needed power parts of SSM2603.

Now it runs stable after every boot.

I think that Analog should review there description and send out a new SSM2603 datasheet.

Like you, I have also problems about reading the register values with I2C interface.
It always return 0x97 ?? But this is solved by using shadow registers instead. This also gives less traffic on the I2C line.

Again thanks for your solution - I am really thankful.

Hi MaxPof,

i work with the brother, SSM2604, and had very occasionally after first power/boot problems. So i followed your and SSMadsen hint of first set R6 D7=1=whole chip power down, followed by all other registers, but then from your picture above you go R9 D0=1=activate digital core, and then R6 D7=0=whole chip power up (and some other power ups) but this is rather unlogically as VMid is generated by R6 D7=0, which needs to be some milliseconds before R9 D0=1=activate digital core.  So i do not really understand why your (MaxPof's) example works, because for that the datasheet is clear:

3. As described in the Digital Core section of the Theory of
Operation, insert enough delay time to charge the VMID
decoupling capacitor before setting the active bit [Register
R9, Bit D0].

I would expect that my SSM2604 requires the same as the SSM2603. As some of my problems only happened sparsely after first boot, i also introduced a power cycle before the initialization by removing the AVDD/DVDD 3v3 supply for a moment, but i discovered that the pullups on i2c (3v3) and/or if my i2s master is already giving clock, voltage "leaks" in and AVDD/DVDD does only drop to ~1v1. I even managed to write the registers (and most of the time got the codec working fine) without AVDD/DVDD, because fast i2c writes raised that voltage to ~1v9 and just right after the writes apply 3v3 but that was just a test, i now apply 3v3 before register writes.

I just wanted to leave that comment here for others, who also wonder about that "nasty" codec.

Hello SteffenV,

Thanks for your comments. Your observations about removing the power (power cycling) and then finding the part works and registers are all set is spot on. This is a problem that a decade or so ago was not a problem. Parts were high enough power draw where the pull-ups of an I2C line would not be anywhere significant enough. What is happening is that the max voltage of the pin is being violated. Max voltage is always specified using IOVDD. So usually something like IOVDD+0.3V. 

Well, think about it,... if IOVDD = 0 then the max voltage on the pin is 0.3V !! What happens then is the ESD protection circuits turn on and connects the pin to the internal power bus. now the part is trying to be powered up via the pin's ESD circuit and the I2C pull up outside of the part. A I mentioned, years ago this was not a problem but with the advent of all these modern super low powered parts it is now able to at least keep the part partially alive!

I have personally seen some of our low powered DSPs retain register settings and memory contents after a power cycle because things like SPI SS pin pull ups and clocks being applied to the part from other sources. 

Once a few years back when I was working on the characterization of the PDM to I2S converter, super low power part. I found that I could power down the part and it would continue to function just fine with absolutely no power!!! It is able to work with just the power from the I2S clocks being applied to it!! I would not recommend this but it is a reminder to use things like level shifters to remove signals if a design is setup to be able to cycle the power or shut off is other things in the design are still on. This is done a lot in the automotive world. You shut off the radio but there are still signals going to it from other places. 

Dave T