Post Go back to editing

[SOLVED] SSM2603 right output offset issue


I try to use the SSM2603 chip on Zybo Z10 board for a month now and I still have the same problem: if I try to play a sinewave, the output signal look like that: (blue=right, yellow:left)

I triple check everything:

-My i2s input signal is OK, two's complement on 24bit:

(sorry, I only have a small part due to my logic analyzer)

I try to configure it with 2 method:

I2C IP based on this

And software from the zynq7 processing system like here:

Here is the soft config:

If I try to swap the right/left output channel (by changing the LRSWAP bit on Reg7), the problem stay on the right channel (but my input signal is well swap)

All clock are verified.

I try to read all the register after a config and they are all right configured.

Well there is just a little thing: if I send any register address to read, the SSM send me back the R0 register value each time. I have to ask to read 10 byte for the SSM to send me the first 10 registers value. It's not how I understand the read function of i2c but anyway...

And finally, here is the I2S and I2C transaction:



My main concern is that if I do a lot of resets, eventually it's gonna work fine... So I suspect a bad config but I can't figure it out

Thanks for your help

Changed title to [SOLVED]
[edited by: MaxPof at 9:41 AM (GMT -5) on 7 Dec 2022]

    Sooooo, I finally found the problem after month of struggle!

    So it turned out that the problem came from the SSM, not from my code...

    First, I finally identify that the problem only occur when I was configuring the SSM the first time after booting.

    If I reconfigured it later, without powering down to the board (and the codec), it worked every time.

    I validated this theory by calling the configuration function twice in a row: no more problems.

    So after some empirical tests, I finally found the fault register: R06 (power management)

    Unlike what is written on the datasheet:

    "Enable all of the necessary power management bits of
    Register R6 with the exception of the out bit (Bit D4).

    You have to leave the default values! (everything power down except OSC and CLKOUT bits).

    Here is my code:


    I haven't had any problems since. Tested on a dozen zybo (Z10 and Z20).

    I don't know if I'm the only one who had this problem.

    I hope it can help someone else and save you wasting as much time as me on this codec...

  • Hi MaxPof

    Thanks for your solution !!
    You are absolute correct! There is an error in the manual for SSM2603, about how to initiate the registers,
    or a very very bad description!

    I have been working with this problem on/off for about 3/4 year !
    Sometimes the codec start up fine and other times not - where you get this "broken" sinus signal - and VMID ends up at 3.3 V not 1.65 Volt as excepted.

    I follow your solution (almost) setting all power pin in reg. 6 to 1 - also setting Hole chip to "power down", (which is rather unlogic ally).
    Making my settings to other registers,  - and then after the a times delay at about 100 msec power up the needed power parts of SSM2603.

    Now it runs stable after every boot.

    I think that Analog should review there description and send out a new SSM2603 datasheet.

    Like you, I have also problems about reading the register values with I2C interface.
    It always return 0x97 ?? But this is solved by using shadow registers instead. This also gives less traffic on the I2C line.

    Again thanks for your solution - I am really thankful.