ADAU1701 output cracking sound when no input

Hi

I have met a problem that, when the input signal to ADAU1701 is muted, ADAU1701 will output a strange cracking noise. It works fine and no any issue when normal playing. And I have tried to monitor the input and output signal, can confirm that the noise is from 1701. And one point that, this cracking noise might happen more frequently when the system temperature is high, not so high, about 60 C degree. 

The following the system diagram, and input/output are I2S. System frequency is set to 192KHz, input and output frequency is 176.4KHz.

And this is the circuit on our board

the recorded cracking noise

Please help.

Best Regards

Frank



updated noise file
[edited by: zpl at 6:38 AM (GMT -4) on 1 Apr 2021]
  • 0
    •  Analog Employees 
    on Apr 2, 2021 6:27 PM 8 days ago

    Hello Frank,

    This is most likely errors in the signal transmission of the data. I need to know more info about the clocking.

    Where does the master clock come from?

    What master clock is being used in the I2S source?

    What device is the clock master for bit clock and LRCLK?

    Do you have any damping resistors on the LRCLK and Bit Clock lines like you have on the I2S Data line?

    Then what is also very important is the PCB layout. This can significantly cause signal integrity issues so it would be good to see your layout and the PCB stackup details. 

    Dave T

  • Hi Dave, 

    Thanks for the reply. 

    The MCLK and I2S signal come from an ARM chip Amlogic A113X, and MCLK is 22.579MHz, and BCLK is 11.289MHz, LRCLK is 176.4KHz. DATA is standard I2S.

    The I2S signal come from A113X, and through a 74HC244 (a switch IC, to select different I2S source to 1701), and then through a 10Ohm resistor, to the 1701. In the circuit, the nodes DAC-SCLK/DAC-LRCLK/SRC-MCLK are connected to the switch chip, and also to the DAC chip. A113X is I2S master, 1701 and DAC are I2S slave.

    And in the demo audio file when the noise happened, the music reached end and no special operations on hardware. Should be only the I2S data goes to 0.

    For the PCB layouts, it has 2 layers, I've generated a picture, please check if it's enough.

    Best Regards,

    Frank

  • 0
    •  Analog Employees 
    on Apr 6, 2021 11:05 AM 4 days ago in reply to zpl

    Hello Frank,

    You are most likely getting bit errors from reflections and timing issues between the bit clock and the data. since it looks like you are using the serial ports for both inputs and outputs I suggest that you run the 1701 serial output port as a master. This reduces the delay of the bit clock to the data coming out of the part. 

    The biggest issue you have is that your PCB is only two layers and you do not have ground and power planes. If you enter this into a signal integrity software simulation and analysis tool it will come back and say the transmission line impedance is undefined. You MUST have four layers if you are using the serial port and if you are trying to run at 176kHz fs it is even more important. 

    I suggest you also look at the PCB Considerations section of the ADAU1452 datasheet for layout concepts of how to connect bypass caps to the part and the power and ground layers. The PCB and layout details are near the end of the datasheet. 

    Thanks,

    Dave T 

  • Hi Dave,

    Thanks for the detailed explanation and information, we'll do more further testing. 

    Best Regards,

    Frank