Please let me ask how to configure PLL and Clock when the sampling rate is lower than 32kHz.
For example, when sampling rate is 16kHz on the ADAU1978,
how can we decide SAI_CTRL0.FS and PLL_CONTROL.MCS values, and MCLKIN frequency?
Depending on the sampling rate that can be set on SAI_CTRL0.FS[2:0],
the PLL_CONTROL.MCS[2:0] should be set based on the Table 9 "Required Input Master Clock Frequency for Common Sample Rates" in the data sheet,
But there are not descriptions for low sampling rates.
ADAU1978 data sheet (rev.A)