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Trimming or Minimizing the DC Offset of AD1852

I am measuring about -53mV at both the channel of outputs of the opamp for OUTPUT BUFFERS AND LP FILTER of the AD1852 DAC.

this value is about typical value given in the datasheet.

Is there a method to trim or minimise this DC offset for AD1852?

I have another Gain stage of 10x after the DAC block, so I ended up with a dc offset of about -0.5V.

I am thinking of avoiding coupling capacitor to between the DAC block and the Gain stage.