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ADAU1361 DC Offset


we have used the ADAU1361 in a product that will be operational this year and we are quite happy with the way it works. We are pairing it with a Linux box to capture analog audio and doing our captures using the ADI driver adjusted to run ou our box. Our arrangement is multi purpose - we plan to use line signals and microphone with the device, but for now our query is for line level signals coming from a PC computer, Cell phone or TV set. BIAS voltage is turned off. 

After performing some recordings to check audio capture quality we came accross a slight DC offset in the ending stereo signal, which can be observed in the attached pictures - we use Audacity to exhamine raw stereo captures coming from the chip. As recommended by looking into ADAU1361 forum posts, we have done all our captures in S32_LE @ 48kHz, as this seems to be the most functional combination for this chip's driver.

I'm sharing schematics and I would like to understand why we observe this DC offset. In our processing we need to downmix to mono and a DC offset will increase noise performance severely.

We appreciate any input on this.