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AD1937 - does it support 8kHz



		

			

									
					    song
					
							

			
				
									
											
			
			
				
    
			
			
			    	
			                    
                
				                on Aug 12, 2011 
				
			
			
		
    

				
		
    
		    		    
		    
		    	
			
    Hello,
    
 
    I am using AD1937, I need to 8kHz sampling frequency application with AD1937 but first page in the manual  said that it supports 8kHz to 192kHz.
    
 
    But I can't find how to set register to use for 8kHz.
    
 
    How can I set AD1937 to support 8kHz?
    
 
    Thanks.
    
 
    Songhee.
    
								
    

				
							AD1937.pdf
					
		
    
			
						
									
									
						
						
			
			
			
			
		
    

        
        

					
    
			
    


    


	
    
		
	
    















    
	
    
	
    
					



			








	
	
	
	



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      •  Analog Employees  
      
            
			                            
                        
                on Sep 1, 2011 6:27 AM
            
            
					
      
	
      

		
		
      
					
      Hi Songhee,
      
 
      I apologize that the settings for the AD1937 are confusing.
      
 
      The MCLKI pin functionality bits (0x00 [2:1]) should be set according to the closest correct multiplier based on the formula:
      
 
      MCLK Freq = (48 kHz window factor of Fs) * (MCLKI multiplier setting in 0x00 [2:1]).
      
 
      The (48 kHz window factor of Fs) is the factor such that when Fs is divided by 1, 2 or 4, the resulting factor lands in the window between 32 and 48 kHz.
      
 
        
  
      • Fs = 32, 64 or 128 kHz yields a factor if 32 kHz.
        • 
  
      • Fs = 44.1, 88.2 or 176.4 kHz yields a factor if 44.1 kHz.
        • 
  
      • Fs = 48, 96 or 192 kHz yields a factor of 48 kHz.
        • 
 
      
 
      The MCLKI /XI pin finctionality bitfield sets the internal workings of the AD1937 PLL to provide the correct internal clocks for both the ADCs and DACs. This is a separate setting from the Sample Rate (Fs) selection.
      
 
        
  
      • If you are using a 24.576 MHz clock and 48 kHz Fs, set the bits to 10 (512 multiplier).
        • 
  
      • If you are using a 12.288 MHz clock and 128 kHz Fs, set the bits to 01 (384 multiplier).
        • 
  
      • If you are using a 22.579 MHz clock and 88.2 kHz Fs, set the bits to 00 (256 muliplier).
        • 
 
      
 
      The DAC and ADC clock source selections (0x01 [1] and [0]) should both be set to 0 (PLL clock) if the PLL is to be used.
      
 
      The DAC and ADC Sample rate windows (0x02 [2:1] and 0x0E [7:6]) should be set according to the desired Fs.
      
 
      Best regards,
      
 
      Coleman
      
			
      

		
		
		
		
	
      
	
      
		
      
			
		
      
	
      
	
      
		
						
						
				
						
				
				
		
		
      
			
		
      
	
      

      

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													0
							
			
				
									
							        
			
			
			
      •  Analog Employees  
      
            
			                            
                        
                on Sep 1, 2011 6:27 AM
            
            
					
      
	
      

		
		
      
					
      Hi Songhee,
      
 
      I apologize that the settings for the AD1937 are confusing.
      
 
      The MCLKI pin functionality bits (0x00 [2:1]) should be set according to the closest correct multiplier based on the formula:
      
 
      MCLK Freq = (48 kHz window factor of Fs) * (MCLKI multiplier setting in 0x00 [2:1]).
      
 
      The (48 kHz window factor of Fs) is the factor such that when Fs is divided by 1, 2 or 4, the resulting factor lands in the window between 32 and 48 kHz.
      
 
        
  
      • Fs = 32, 64 or 128 kHz yields a factor if 32 kHz.
        • 
  
      • Fs = 44.1, 88.2 or 176.4 kHz yields a factor if 44.1 kHz.
        • 
  
      • Fs = 48, 96 or 192 kHz yields a factor of 48 kHz.
        • 
 
      
 
      The MCLKI /XI pin finctionality bitfield sets the internal workings of the AD1937 PLL to provide the correct internal clocks for both the ADCs and DACs. This is a separate setting from the Sample Rate (Fs) selection.
      
 
        
  
      • If you are using a 24.576 MHz clock and 48 kHz Fs, set the bits to 10 (512 multiplier).
        • 
  
      • If you are using a 12.288 MHz clock and 128 kHz Fs, set the bits to 01 (384 multiplier).
        • 
  
      • If you are using a 22.579 MHz clock and 88.2 kHz Fs, set the bits to 00 (256 muliplier).
        • 
 
      
 
      The DAC and ADC clock source selections (0x01 [1] and [0]) should both be set to 0 (PLL clock) if the PLL is to be used.
      
 
      The DAC and ADC Sample rate windows (0x02 [2:1] and 0x0E [7:6]) should be set according to the desired Fs.
      
 
      Best regards,
      
 
      Coleman
      
			
      

		
		
		
		
	
      
	
      
		
      
			
		
      
	
      
	
      
		
						
						
				
						
				
				
		
		
      
			
		
      
	
      

      

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