AD1937 - does it support 8kHz


I am using AD1937, I need to 8kHz sampling frequency application with AD1937 but first page in the manual  said that it supports 8kHz to 192kHz.

But I can't find how to set register to use for 8kHz.

How can I set AD1937 to support 8kHz?



  • Hi Songhee,

    It is possible to run the AD1937 at 8 kHz; the PLL will not run that slowly and so the PLL must be turned off and the part run in Direct Clocking mode. See the datasheet for more details.

    The register settings are as follows:

    PLLCC0: 0x84 (Enable ADC and DAC, Input 512 x Fs)

    PLLCC1: 0x03 (Clock sources = MCLK: this is Direct Clock mode)

    The system will need to provide an MCLK that is 512 x Fs = 4.096 MHz. If you need to change the sample rate, you will need to provide a different MCLK frequency.

  • Update:

    PLLCC0: 0x81 (Enable ADC and DAC, PLL disabled)

    PLLCC1: 0x03 (Clock sources = MCLK: this is Direct Clock mode)

    Sorry for the confusion.

  • Thanks.

    I tested AD1937 for 8kHz and 16kHz.It works with PLL off, so AD1937 can support between 8kHz to 196kHz at least if MCLK is 512fs in direct MCLK mode. Is it right?

    Thanks again.


  • In typical systems, the sample rates will be either 48 kHz, 96 kHz, or 192 kHz. All of these can be achieved in the direct MCLK mode.

    However, the upper limit of the sample rate is a little bigger than that. You can see in the datasheet that in 512 Fs direct MCLK mode, the maximum frequency of MCLK is 27.6 MHz. This means that you can actually run the system up to 12% faster than the nominal sample rates, if you wish.

  • In the manual, "Note that it is not possible to use a direct clock for the ADCs set to the 192 kHz mode." I should read more carefully..

    Thanks. Your answer is very helpful for me to test for all use case with AD1937.

    But I have one more thing to be clear in PLL setting.

    Ih 192kHz case, should I apply 48kHz*512 clock to MCLK in, set  Input 512 in PLL Clock Control 0, PLL clock in PLL Clock Control 1, set sampling rate 128kHz/176.4kHz/192kHz in DAC Control 0?

    I am a little bit confused at how to set PLL target frequency.

    Can you please explain to me about the pll clock control?

    Hmm, for example, master clock rate setting in PLL and Clock Control 0 Register means the frequency of MCLK in or target frequnecy of PLL out?

    How does it determin the target frequency of PLL?

    Thanks again.