That sounds fine. If I understand correctly, MCLK = 24.576 MHz will be generated by an external source. Are you going to run both ADC and DAC ports in 16-channel mode? Which part will be generating BCLK and LRCLK? It is not necessary for MCLK to be phase locked with the serial clocks BCLK and LRCLK, but MCLK must never cross edges with them. BCLK and LRCLK must be properly timed against each other, however. I would recommend that you use one of the AD1937 ADC ports as a BCLK and LRCLK Master for the whole system.
There is an eval board for this part: EVAL-AD1937AZ if you would like to test the modes before building your board.