ADMP421 bias in output signal.

If you are getting an output from the ADMP421 microphone through the ADAU1761, then the problem is likely not caused by soldering or the pad layout.

When you say that you are also using an "external microphone", do you mean an analog mic connected to the ADAU1761's analog inputs? The ADMP421's digital output does have a small dc bias introduced by the modulator. This is deliberately included to prevent modulator idle tones and it's expected that this dc bias will be removed in the codec. The ADAU1761's ADCs have a high pass filter at 2 Hz (for fs = 48 kHz) and I believe that filter is in the signal path for both the analog and PDM inputs (I'll try to confirm that tomorrow). Do you have this high-pass filter enabled in your design?

Hi Jerad,

Thanks for the prompt reply. I did not have the high pass filter enabled. When I did, I noticed it took a long time for the bias to drop although I did notice an improvement in the audio quality. I am using a signed 16 bit word to hold the 24 bit audio samples which has the least significant 8 bits removed. When I first power up the system, I am measuring a bias of 10200. After 34 minutes, I am measuring a bias of 3166. This seems like a very long time for the filter to settle and is not acceptable for our application. Is it possible to use a filter block in the dsp schematic to do the same thing as the high pass filter but much quicker or is there a register setting that I am missing that would speed up the ADCs high pass filter?

Are you using the digital or analog outputs from the ADAU1761 in your system? If you're using the analog outputs, then a dc offset shouldn't be much of an issue because the analog outputs will most likely be ac-coupled (unless you're using the virtual ground with the headphone outputs). If you're using the digital outputs, are you setting the ADAU1761 to output a 16-bit word or are you truncating the data in a subsequent processor? If you're reducing the bit depth in another processor, you may want to consider dithering the data, rather than just truncating.

You could certainly implement a high pass filter in your SigmaStudio project to filter out these low frequencies. You wouldn't necessarily have to set the filter corner as low as the ADAU1761's built-in filter, since the microphone's low frequency corner is at 100 Hz. I'm not sure why the time constant of that high pass filter seems to be so long. If you have additional questions about that, you may want to ask those in the SigmaDSP section of EngineerZone: https://ez.analog.com/community/dsp/sigmadsp

One more point that I forgot to mention in my last post...I did confirm that the ADAU1761's high pass filter is implemented digitally, so it will work for both analog inputs and digital microphones. The latest test you described above already indicates this, but I just wanted to post it here explicitly (either for you or whoever might read this thread in the future).

If anyone else is interested in seeing the follow-up discussion about the ADAU1761's high pass filter, here's a link to that in the SigmaDSP section of EngineerZone: https://ez.analog.com/message/44073#44073

Hi Jerad,

After some more trouble shooting, I've found out a few more things and I was wondering if this might be what is causing this issue. Although my system is using only the one ADMP421 microphone, when I spy on the I2S bus, I am seeing samples on both channels that have to be coming from the same source. I have an idea that our problems with the microphone pcb layout may have caused the microphone to output samples on both channels but what happens when it is forced to output samples at twice the rate the clock is set for? Does the microphone need the half cycle of the I2S frame clock it is not transmitting to properly acquire the sample? I get the impression I have inadvertently created a low pass filter in the signal chain.

I thought that your question about seeing data in both channels in your codec warranted its own thread, so I opened a new one here and answered the question: https://ez.analog.com/message/44631#44631

Your PDM microphones are being clocked at the correct rate. A 3.072 MHz clock, for example, can be used to clock either one or two PDM mics that share the same data line. This is because each mic uses only one clock edge, so the clock rate doesn't have to change to support two mics instead of just one.

If you're still having issues with your board, feel free to post your schematic here and I'll be happy to review it. You could post it either in the public forum or in a private message to me.