AD1939 - Clocks questions

Hello,

I'am using an AD1939 codec and I have a crystal on my board which generates 12,288 MHz (256 x Fs in my case, since I'll use only 48 kHz as a sample rate) and this crystal is connected to the MCLKI/XI pin of the AD1939.

All the systems is connected to a FPGA, which will receive the 12,288 MHz as well.

In my registers, I am going to put the MCLKI/XI for the PLL input in PLL and Clock Control register 0.

Here are my questions :

For the PLL and Clock control register 1, what is exactly the difference between PLL Clock and MCLK for the DAC and ADC source ?

The PLL isn't supposed to generate the MCLK ? In my case, putting both in PLL Clock would be OK ?

About the LRCLK, what is the difference between Slave and Master ? Do I have to provide a 48 kHz signal in master mode or is it self-generated from my MCLK since I provide it with the MCLKI/XI ?

If I have to generate a 48 kHz signal, do you think that generating it from the FPGA would be OK or it would jitter the signal so badly it wouln't be usable ?

About the BCLK, I'm planning to put in Master mode and to put in Internally Generated. If I get it right, it will be generated and I don't have to connect anything on the BCLK ?

They are maybe "silly" questions, and I apologize, I'm new in design creation :-)

Thanks in advance,

Florent

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  • 0
    •  Analog Employees 
    on May 15, 2012 4:41 PM

    Hi Florent,

    Just to be thorough, let me confirm that you are taking the MCLKO/XO pin back to the crystal, through a 100 ohm resistor. How are you getting an MCLK signal to the FPGA? Any crystal loop is a delicate interface; I would not recommend driving multiple loads with the MCLKO/XO pin directly. A buffer would be a good idea if the signal does not look like it has good integrity.

    The PLL Clock vs. MCLK selection determines whether the codec's internal counters are getting their signal from the PLL or directly from the MCLKI pin. If you use Direct Clocking, you must use a frequency that is 512 x Fs; 48 kHz sampling rate would require 24.576 MHz MCLK. Using the PLL will improve the performance of the system if there are questions about the quality of the MCLK stability. Using the PLL also gives you the option of clocking the AD1939 from an LRCLK signal instead, requiring no MCLK at all. Using PLL Clock as the Clock Source for both ADC and DAC sections would be fine.

    With regards to your Master/Slave question: the AD1939 ADC and/or DAC can generate its own LRCLK and BCLK in Master mode, if the chip is driven with an external MCLK. Or the AD1939 serial audio ports can run in Slave mode, where the LRCLK and/or BCLK are driven from the outside. I have seen FPGAs generate high quality clocks, however, by using the AD1939 as a source for LRCLK and BCLK, you would have the best opportunity for optimal performance.

    The BCLK-less mode that you are describing is generally intended for a design that would suffer from having any high frequency clocks on the board; you have talked about using an MCLK which would usually be 4x BCLK. In this case, I would also want to use a BCLK to lock the send and receive ports together, maximizing the system integrity. If you were to use a PLL mode where an LRCLK is the clock source, you would be able to remove both MCLK and BCLK, and you could run the AD1939 in the mode that you describe: one of the LRCLK ports would be a Slave and that port would be the Clock source for the PLL; the Loop Filter is different for this mode, please consult the datasheet for the correct RC values. Also in this mode, the appropriate BCLK would be a Master set to Internally generated. In this mode, the FPGA in your system would also need to be internally generating a BCLK in order to clock the data back and forth between the devices. The timing here is very important, since the BCLK is hidden. This type of design is only recommended in the case where EMI must be kept to a minimum; most designs use both MCLK and BCLK and with the proper system design (single solid ground plane, proper termination of clock and data lines, etc), they pass emissions tests easily.

    Please let me know if you need more explanation. Feel free to download the User Guide for the EVAL-AD1939AZ evaluation board; boards are available on the product page if you need one to help with your system design.

    Best regards,

    Coleman

    PS there are no silly questions.

Reply
  • 0
    •  Analog Employees 
    on May 15, 2012 4:41 PM

    Hi Florent,

    Just to be thorough, let me confirm that you are taking the MCLKO/XO pin back to the crystal, through a 100 ohm resistor. How are you getting an MCLK signal to the FPGA? Any crystal loop is a delicate interface; I would not recommend driving multiple loads with the MCLKO/XO pin directly. A buffer would be a good idea if the signal does not look like it has good integrity.

    The PLL Clock vs. MCLK selection determines whether the codec's internal counters are getting their signal from the PLL or directly from the MCLKI pin. If you use Direct Clocking, you must use a frequency that is 512 x Fs; 48 kHz sampling rate would require 24.576 MHz MCLK. Using the PLL will improve the performance of the system if there are questions about the quality of the MCLK stability. Using the PLL also gives you the option of clocking the AD1939 from an LRCLK signal instead, requiring no MCLK at all. Using PLL Clock as the Clock Source for both ADC and DAC sections would be fine.

    With regards to your Master/Slave question: the AD1939 ADC and/or DAC can generate its own LRCLK and BCLK in Master mode, if the chip is driven with an external MCLK. Or the AD1939 serial audio ports can run in Slave mode, where the LRCLK and/or BCLK are driven from the outside. I have seen FPGAs generate high quality clocks, however, by using the AD1939 as a source for LRCLK and BCLK, you would have the best opportunity for optimal performance.

    The BCLK-less mode that you are describing is generally intended for a design that would suffer from having any high frequency clocks on the board; you have talked about using an MCLK which would usually be 4x BCLK. In this case, I would also want to use a BCLK to lock the send and receive ports together, maximizing the system integrity. If you were to use a PLL mode where an LRCLK is the clock source, you would be able to remove both MCLK and BCLK, and you could run the AD1939 in the mode that you describe: one of the LRCLK ports would be a Slave and that port would be the Clock source for the PLL; the Loop Filter is different for this mode, please consult the datasheet for the correct RC values. Also in this mode, the appropriate BCLK would be a Master set to Internally generated. In this mode, the FPGA in your system would also need to be internally generating a BCLK in order to clock the data back and forth between the devices. The timing here is very important, since the BCLK is hidden. This type of design is only recommended in the case where EMI must be kept to a minimum; most designs use both MCLK and BCLK and with the proper system design (single solid ground plane, proper termination of clock and data lines, etc), they pass emissions tests easily.

    Please let me know if you need more explanation. Feel free to download the User Guide for the EVAL-AD1939AZ evaluation board; boards are available on the product page if you need one to help with your system design.

    Best regards,

    Coleman

    PS there are no silly questions.

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