Looking for detailed info on adau1961 spi protocol

The datasheet has very little data on this protocol.

It does not seem to mention the inactive clock polarity.

I have assumed that it is low (from the very vague spi protocol image)

The MISO data should be read on the rising edge.

I assume to read register 0x402d I would:

clock the enable low three times (with a 1 msec delay on edge changes)

pull the enable low

send 0x01     //the address plus the read bit

send 0x40

send 0x2d

drive the master with a dummy write and read the slave.

drive enable high

So when I do this the ada1961 pulls the MISO data line low just after the 0x2d and that's all I get.

I know this register defaults to  0xAA from the data sheet.

Any help would be appreciated!

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  • Hello Dan,

    Your method is correct, and the protocol appears to be correct as well. There is one small detail, however. When the device powers up, there is only one register that is accessible via the control port: 0x4000, the Clock Control register. In order to access any other registers, you must first enable the core clock by setting a bit in this register.

    [EDIT] Actually, the register at addresses 0x4000 and 0x4002 are the two registers that are accessible at startup.

    Here's the corresponding section of the datasheet that describes it in more detail. It's on page 36, for reference.

    The control port is capable of full read/write operation for all addressable registers. The ADAU1961 must have a valid master clock in order to write to all registers except for Register R0 (Address 0x4000) and Register R1 (Address 0x4002).

    So, the core clock must be present inside the chip in order to read or write any register. In order to enable the core clock, you need to enable the COREN bit [0] of the 0x4000 register.

    Here are some additional tables from the datasheet describing this detail (click on each picture to enlarge it).

    So, I will make a small update to your SPI communication sequence:

    clock the enable low three times (with a 1 msec delay on edge changes)

    • clock the enable low three times (with a 1 msec delay on edge changes) to enable SPI mode
    • pull the enable low
    • send 0x00 // the address plus write bit
    • send 0x40
    • send 0x00
    • send 0x01 // this enables the COREN bit
    • pull enable high // end of first write transaction
    • pull enable low // begin read transaction
    • send 0x01     //the address plus the read bit
    • send 0x40
    • send 0x2d
    • drive the master with a dummy write and read the slave.
    • drive enable high

    This should get you the 0xAA you're looking for.

    By the way, to answer your other question, the ADAU1961 uses SPI Mode 3, where CPOL = 1 and CPHA = 1. This can be ascertained by looking at the SPI timing diagrams closely, but you're correct that they are vague. I will try to make this more clear in future datasheet revisions.

    For reference:

    (image from Wikimedia Commons)

    (image from Total Phase)

    Message was edited by: BrettG - Clarified which registers are available at startup

Reply
  • Hello Dan,

    Your method is correct, and the protocol appears to be correct as well. There is one small detail, however. When the device powers up, there is only one register that is accessible via the control port: 0x4000, the Clock Control register. In order to access any other registers, you must first enable the core clock by setting a bit in this register.

    [EDIT] Actually, the register at addresses 0x4000 and 0x4002 are the two registers that are accessible at startup.

    Here's the corresponding section of the datasheet that describes it in more detail. It's on page 36, for reference.

    The control port is capable of full read/write operation for all addressable registers. The ADAU1961 must have a valid master clock in order to write to all registers except for Register R0 (Address 0x4000) and Register R1 (Address 0x4002).

    So, the core clock must be present inside the chip in order to read or write any register. In order to enable the core clock, you need to enable the COREN bit [0] of the 0x4000 register.

    Here are some additional tables from the datasheet describing this detail (click on each picture to enlarge it).

    So, I will make a small update to your SPI communication sequence:

    clock the enable low three times (with a 1 msec delay on edge changes)

    • clock the enable low three times (with a 1 msec delay on edge changes) to enable SPI mode
    • pull the enable low
    • send 0x00 // the address plus write bit
    • send 0x40
    • send 0x00
    • send 0x01 // this enables the COREN bit
    • pull enable high // end of first write transaction
    • pull enable low // begin read transaction
    • send 0x01     //the address plus the read bit
    • send 0x40
    • send 0x2d
    • drive the master with a dummy write and read the slave.
    • drive enable high

    This should get you the 0xAA you're looking for.

    By the way, to answer your other question, the ADAU1961 uses SPI Mode 3, where CPOL = 1 and CPHA = 1. This can be ascertained by looking at the SPI timing diagrams closely, but you're correct that they are vague. I will try to make this more clear in future datasheet revisions.

    For reference:

    (image from Wikimedia Commons)

    (image from Total Phase)

    Message was edited by: BrettG - Clarified which registers are available at startup

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