I could be wrong and it may be a register setting I haven't got right. It appears that the ADAU1361 clocks itself from the pin in master mode rather than an internal copy. If true this is problematic if the load cannot be well constrained. In our application we connect the serial audio port via a ribbon cable to another board, this is not always of the same length for reasons I won't go into. On the prototype Rev.A board we did not have a series termination and suffered a poor signal at the receiving FPGA, a situation that could be cured by resampling the BCLK with a 50MHz clock, removing the reflection.
We decided in any case to put in a termination on the Rev.B board as we had a minor mechanical issue to fix. Longer ribbon cables prevent the device from generating a correct serial output with the series termination on BCLK with a tidy signal at the FPGA. It can be clearly seen on a scope that the reflection seen at the BCLK pin can be moved to effect proper operation by changing the series termination. Clearly if my conclusion is correct then this is problematic if I cannot guarantee to keep the position of the reflection out of harms way at the ADAU1361 BCLK pin over production spread.
Please confirm or suggest otherwise. Dejitter is off BTW.