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ADAU1361 BCLK pin

I could be wrong and it may be a register setting I haven't got right. It appears that the ADAU1361 clocks itself from the pin in master mode rather than an internal copy. If true this is problematic if the load cannot be well constrained. In our application we connect the serial audio port via a ribbon cable to another board, this is not always of the same length for reasons I won't go into. On the prototype Rev.A board we did not have a series termination and suffered a poor signal at the receiving FPGA, a situation that could be cured by resampling the BCLK with a 50MHz clock, removing the reflection.

     We decided in any case to put in a termination on the Rev.B board as we had a minor mechanical issue to fix. Longer ribbon cables prevent the device from generating a correct serial output with the series termination on BCLK with a tidy signal at the FPGA. It can be clearly seen on a scope that the reflection seen at the  BCLK pin can be moved to effect proper operation by changing the series termination. Clearly if my conclusion is correct then this is problematic if I cannot guarantee to  keep the position of the reflection out of harms way at the ADAU1361 BCLK pin over production spread.

     Please confirm or suggest otherwise. Dejitter is off BTW.

  • Hi Dave,

    Sorry that it took me a few days to get back to you on this. I checked with some designers and I was waiting for their responses.

    The information that I have received so far is as follows:

    • The BCLK, if in master mode, clock out at the pin, and that version is then copied to the flop to then clock out the data. The reason for doing this was to make sure that the clock and data lines have their edges synchronized.  If an internal copy of that clock was used, that could lead to a potential set up and hold time violation, which is what the designers were trying to avoid.
    • The I2S "Inter-IC Sound" spec is designed primarily to be used as a data bus between ICs on the same PCB.
      • For this reason, the ADAU1361 digital I/O pins were designed for output loads of around 20 pF and around a 2 mA current drive capability, which is listed in the ADAU1361's specification table in the datasheet.
      • Typically in cases where the signal needs to travel long distances, the I2S bus should travel a short distance over a trace to a buffer, which can then be used to drive the larger loads associated with cables traveling to other boards.
    • Typically on our boards that are designed to drive cables, we use some kind of buffer like the SN74LV125AD (IC buffer, quad three-state ,14 SOIC Texas Instruments).

    I hope this information is helpful. Let me know if you have any other questions.

  • Thanks Brett,

         We have a solution that appears robust because the BCLK frequency is so low we can use a series resistor as high as 150 ohm and resample in our FPGA. The large value resistor effectively decouple the device from the load so that the device is insensitive to the cable (verifyied on a 'scope). This compromised system works over a wide range of boards and cable lengths. I will consider the buffer solution in any other application.

    Regards

    Dave

  • Hi Dave,

    Thanks for the feedback. I hope that setup works well for you. Let me know if you need additional assistance.

  • Confirm – I have the same problem.

    The I2S port is transferred on a ribbon cable:  on one side - ADAU1361 (now Master), on other side - some receivers (including ADV7513) and future sources.

    Series resistor – is 150 Ohms. At smaller value - ADC ADAU1361 don’t work, at bigger value - I2S- port of ADV7513 don’t work …

    Signal ADC_SDATA go to left on some tic of BCLK and ahead front of LRCLK. But distortions of a signal of LRCLK it isn't observed.

    Pin BCLK is very “delicate”. If PLL is used, this pin becomes extremely “delicate”! Don’t to use internal copy of BCLK and to make this pin very weak – it is mistake of AD!

    Best Regards,

    Alexander

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