AD1937 with BF533

Hi, I´m using AD1937 codec with BF533 on my own board. The problem is that DAC is not working. Digital signals are ok but the analog out is always 1.5V. Could anybody suggest me what test could I do?


  • 0
    •  Analog Employees 
    on Oct 10, 2012 10:58 PM

    Hi Ana,

    I will need some other information before I can give you good advice. Are you using the AD1937 in Stand Alone mode? If not, can you please provide your register settings for the AD1937? Are you able to read back the registers to confirm your settings? Can you provide the clock frequencies for MCLK, LRCLK and BCLK, please? Thanks.



  • Hi Coleman,

    I´m not using AD1937.

    I´m setting the register such as shown here:

    PLL_CLK0 = (0x01<<7)+(0x01<<2)

    PLL_CLK1 = default

    DAC0 = 0x00

    DAC1 = 0x01<<4 + 0x01<<5 + 0x01<<6

    DAC2 = 0x00

    DAC_MUTE = 0x00









    ADC0 = 0x00

    ADC1 = 0x00

    ADC2 = 0x01<< 3 + 0x01<<6 + 0x01<<7

    I´m using AD1937 as a master device: MCLK=256*fs, LRCLK=48kHz, BCLK=3,072MHz.

    I´m using a 12.88Mhz external oscillator.


  • 0
    •  Analog Employees 
    on Oct 11, 2012 6:41 PM

    Hi Ana,

    I hope that I am understanding your notation correctly:

    PLL_CLK0: bit 7 [1] and bits 2:1 [10]

        *bit 7 needs to be [1] to activate the AD1937. Neither the ADC nor DAC would work if this was not set to [1]

         *bits 2:1 [10] are setting the MCLK rate to 512xFs. your MCLK frequency of 12.288 MHz requires this be set to [00].

    DAC1: bit 4 [1], bit 5 [1] and bit 6 [1]

         *bits 4 and 5 set the port to Master. This implies that your DAC data source is in Slave mode and will clock out data based on the LRCLK and BCLK supplied by the AD1937. Is this correct? Have you looked at these signals on the board with an oscilloscope, and so they have good integrity?

         *bit 6 sets the BCLK port to internal generation; this mode allows the audio port to operate without connecting BCLK. Internal generation is used in the case where the DAC or ADC port is driven only with LRCLK in Slave mode, BCLK is in Master mode and the BCLK signal is generated inside the AD1937 for use by that port only. This mode saves a clock trace on the pcb.

    ADC2: bit 3 [1], bit 6 [1] and bit 7 [1]

         *bits 3 and 6 set the ADC port to Master mode; it is more common to have the data and clocks both supplied by the port that sources the data.

         *bit 7 performs as described above.

    I would try setting your MCLK multiplier to 256xFs (0x00) and leaving the BCLK source bits at default (0x00). Let me know how you DAC clocks look, attach a screen shot if you can.



  • 0
    •  Analog Employees 
    on Aug 2, 2018 4:41 PM
    This question has been assumed as answered either offline via email or with a multi-part answer. This question has now been closed out. If you have an inquiry related to this topic please post a new question in the applicable product forum.

    Thank you,
    EZ Admin