In the TDM4 mode, does the ADC_DATA pin on the ADAU1361 go tri-state during TDM slots in which it is not programmed to respond?
I want to parallel multiple codecs on the same serial port lines. If the digital outputs don't go high-impedence during other slots, the outputs will conflict.
Optional bonus point question: Is there an equivalent to the ADAU1361 that will do multiple channels? I'm looking for 4-8 channels of single-ended line input and differential line output. SPI control is a must.
Unfortunately, I don't think the ADAU1361 is going to work in your intended use case because there are some missing features and design quirks that make it impossible to put two of these devices in parallel operating on the same TDM stream.
First, and most importantly, the ADAU1361 does not have a "three-state on idle channels" option, so the serial port will simply drive out zeros on inactive channels. This means that, unfortunately, you won't be able to run two of these in parallel and have them share the same TDM line.
Of course, since it is useful from an applications perspective to have three-state logic on the serial data lines (as opposed to the ADAU1361's two-state implementation), that feature has been included in all of the new designs for our next generation of codecs and SigmaDSPs.
The routing of data channels on the TDM stream is a little bit non-intuitive (this is another problem that has been addressed in our newer designs). In two channel mode, the order of the channels on the serial data lines will be as follows:
ADC_SDATA: ADC0, ADC1
DAC_SDATA: DAC0, DAC1
This, of course, makes sense.
However, in TDM4 mode, the channel routing is like this:
ADC_SDATA: ADC0, Inactive channel, ADC1, Inactive channel
DAC_SDATA: DAC0, Inactive channel, DAC1, Inactive channel
This deviates from the "standard", which would look more like this:
ADC_SDATA:ADC0, ADC1, Inactive channel, Inactive channel
DAC_SDATA:DAC0, DAC1, Inactive channel, Inactive channel
The difference between the "first pair" and "second pair" in TDM4 mode can be summed up like this: the "first pair" mode corresponds to the channel mapping I described above, whereas the "second pair" mode looks like this:
ADC_SDATA: Inactive channel, ADC0, Inactive channel, ADC1
DAC_SDATA: Inactive channel, DAC0, Inactive channel, DAC1
You can see that basically the position of the data channels and the inactive channels are swapped.
The "third pair" and "fourth pair" settings only apply to the TDM8 mode of the ADAU1761, which is the "sister" of the ADAU1361, basically pin-compatible and register-compatible but with an included SigmaDSP core. They are not valid in the ADAU1361, and if you use either of those settings, you will simply see no data passing through the serial ports.
Regarding your question on bits per frame... the options available in the register settings were basically selected after analyzing the market and seeing what kinds of settings were required by customers. It was deemed that in most I2S streams, common applications either use:
I wasn't part of the design team, but I imagine that the 24-bit data per channel / 24-BCLK cycles per channel option was not included simply because there was no market demand for that operating mode. Please let me know if the 24/24 mode is something you'd like to use, and I will provide that as feedback to the design team.
I hope this answers your questions.