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AD1896/AD1895 MCLK_I jitter tolerance

Hi,

When external clock signal is supplied to MCLK_I pin of AD1895/96, how much jitter is acceptable for proper operation?

  • Hi,

    Unfortunately, we do not have any characterization data to show the outside range of operation of the AD1895/96 as a function of increasing jitter on MCLK. There is an internal circuit that reduces the jitter from the MCLK input to the BCLK and LRCLK generated by the AD1895/96, but at some point it will stop being effective and the clocks in the part will exhibit a reduced version of the jitter as well.

    Best regards,

    Coleman