SSM2518 Test

Hi All,

somehow I have no luck with testing of a SSM2518 Class-D amplifier. I connected it to a BF527 via SPORT0 according to the attached schematic. The I2C communication works fine but eliciting a sound out of the device fails completely. A 3000 Hz sinus at a sample rate of  24 KHz. serves as test signal. The resolution of this signal is 32 bit. I configured the SPORT of the BF527 to  a clock frequency of 3.072 MHz in stereo frame mode. When the SPORT clocks out the signal the speaker produces a faint noise but no sound. I configured the SSM 2518 in the following way:

register 0x00 value 0x22

register 0x01 value 0x01

register 0x02 value 0x01

register 0x03 value 0x00

register 0x07 value 0xA0

register 0x09 value 0x80

register 0x0A value 0x00

I tried also Mono PCM mode without success. I observed the existence of the MCLK, LRCLK and SDATA signal with an oszilloscope. They are all present. I have following questions:

1. Is it all right to deliver the MCLK signal only for the time, when the SPORT clocks out data or has it to be present immediately after reset ?

2. Is it all right to set bit 5 of register 0x00 without setting bit 7 of register 0x03 in this hardware configuration ?

3. Are there any code examples for this amplifier or similar ones available ?

4. Does anyone has an idea how to find the problem in a systematic way ?

  • 0
    •  Analog Employees 
    on Mar 10, 2013 6:04 PM

    Hi,

    I apologize that the bitfield description in Table 13 for MCS is not clear. Consulting Table 11, the 24 kHz row referenced to 3.072 MHz MCLK requires an MCS setting of b0000. Please try changing your setting for register 0x00 with a value of 0x20. Does this new setting help?

    Regards,

    Coleman

  • Hi,

    thank you for this proposal but this setting does not change something. Another error must be present additionally. I have another problem in understanding the datasheet concerning the clocking options. The datasheet (Rev A, page 14 ) states "...This (internal master) clock signal can be derived from either the MCLK or BCLK pin, depending on the configuration used. ...". The descriptions following this sentence do not clearly include the case where the BCLK pin is used to derive the internal master clock from it or ? If I rightly understand the MCLK Pin always has to be used and the BCLK pin can be used additionally or not ?

  • 0
    •  Analog Employees 
    on May 9, 2013 9:53 PM

    Here is a table that might help with your configuration.

    BCLK_GEN

    NO_BCLK

    Internal BCLK Source

    0

    0

    BCLK Pin

    0

    1

    MCLK Pin

    1

    0

    Generated from divided MCLK pin

    1

    1

    Generated from divided MCLK pin

  • Hi ColemanR,

    thank you for this clarification..after a long time I found the major problem, I configured the SPORT0_TFSDIV of the Blackfin with 32 instead of 31!

    This stupid off-by-one error lead to the effect, that no sound could be heard in nearly all configurations..finally I came in observation of strange side-effects when using slightly different clocks as the SPORT clock as Masterclock to the finding..regards robert