SSM2604 ADC output

We are seeing a new issue in our product in production line related to SSM2604 and this issue is observed in the factory and we have a line down situation because of this issue.

As part of manufacturing flow the factory is verifying the functionality after assembly is done. We are seeing failure with Audio capture functionality of SSM2604 (ADC output). This failure is seen in 1 out of 4 boards in the production line.

Interestingly this issue occurs only once after first power ON, If the board is power cycled, we were not able to reproduce the issue.

We tried to analyze the issue with one of the boards and found that in the failed condition, the RECDAT output is generating a fixed pattern and the waveform captured is attached (ssm2604_data_fail.jpg). The BCLK and RECLRC clocks are respectively 3Mhz and 48kHz which are expected and match the behavior of a working case. But the ADC data out is showing the unexpected behavior as in attached waveform.

I have attached section of schematics (SSM_Sch.JPG) for your reference. Also I have attached the register dump (SSM_Issue.txt) to show the programmed values inside SSM2604. This dump was captured in the failed condition and this matches with the register dump taken in the working case.

Here is the date code read from the package top for your reference:

#1245

88359

  Request you to provide urgent help to debug the issue.

attachments.zip
  • Hello,

    I contacted the applications engineer about your question. Hopefully he should reply soon.

  • 0
    •  Analog Employees 
    on Apr 17, 2013 11:42 PM

    Hi,

    We are addressing this issue offline. Please be aware that there is a control register programming sequence that must be followed:

    CONTROL REGISTER SEQUENCING

    1. Enable all of the necessary power management bits of Register R6 with the exception of the out bit (Bit D4). The out bit should be set to 1 until the final step of the control register sequence.

    2. After the power management bits are set, program all other necessary registers, with the exception of the active bit [Register R9, Bit D0] and the out bit of the power manage-ment register.

    3. As described in the Digital Core Clock section of the Theory of Operation, insert enough delay time to charge the VMID decoupling capacitor before setting the active bit [Register R9, Bit D0] .

    4. Finally, to enable the DAC output path of the SSM2603, set the out bit of Register R6 to 0.

    In short, VMID must be at full voltage before you enable the digital core.

    Best regards,

    Coleman

  • 0
    •  Analog Employees 
    on Aug 2, 2018 4:49 PM
    This question has been assumed as answered either offline via email or with a multi-part answer. This question has now been closed out. If you have an inquiry related to this topic please post a new question in the applicable product forum.

    Thank you,
    EZ Admin