For my Thesis on Audio processing. I want to develop a test bed to demonstrate DSP logic's(e.g. starting will be from LMS and then moving to complex logics) in real time. The test bed will consist of atleast 64 speakers (arranged in 2-D) and atleast 32 Mics(arranged in 2-D). I had already ordered one ADAU1446 evaluation board from ADI. One ADAU1446 is capable of controlling 8 channels audio In and 16 channels audio out. So I am planning to stack 4 of ADAU1446 evaluation boards. My questions are following:-
1) Is this design of stacking 4 ADAU1446 feasible? What will be the possible challenges?
2) I think I also need master FPGA to synchronise 4 slave ADAU1446. Can you please point to some reference study material in this context?
3) All the audio IN data from audio codec will be routed to centralised DSP chip(ADAU1446 or sharc.) for DSP and then the digital output will be routed to DAC in audio codec. All this will use I2S bus. Is it feasible in real time?
4) Can you please recommend some FPGA for this purpose?
Thanks for advice