ADAU1961 I2S master mode

Hi,

I am trying to use the ADAU1961 as simple stereo ADC with external MCLK (12.288MHz) with 256×Fs and 48kHz sample rate.

If I set up the device to generate the BCLK and LRCLK (master mode operation), the clocks are correct but the data coming out changes

on both edges of the BCLK.

If I enable only one channel, I see data (changing on both edges of BLCK) during both level of LRCLK. (see the attached picture)

If I change the bus mode to slave, every other settings not affected, and I feed the BLCK and MCLK to the ADAU1961, the data is correct,

changing only on falling edge and the audio sounds good.

The settings:

R0 (0x4000) : 0x01

R15 (0x4015) : 0x01

R16 (0x4016) : 0x00

R17 (0x4017) : 0x00

R18 (0x4018) : 0x00

R19 (0x4019) : 0x31 (one ADC channel is enabled)

Thanks for your help.

attachments.zip
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  • 0
    •  Analog Employees 
    on Oct 14, 2013 6:39 PM

    Hello BartaG,

    The internal clock will not be coming from the BCLK pin in master mode but you did expose some possible weakness in your PCB layout. Yes, proper termination of the clock lines is of huge importance and solved your issue. What was probably happening is these reflections were possibly either creating crosstalk to other clock lines but most likely it was causing a fair amount of ground bounce, or ground noise. I suggest you check the decoupling of the part very carefully. It is a subtle thing but makes a big difference. Having a .1uf cap close to the power pins is just the start. Then the connections to the power and ground planes have to be done such that the cap is between the part and the vias to the planes. We have seen problems when the via is placed between the part pin and the cap. Yes, the trace is still very short but it reduces the effectiveness of the decoupling cap. If you then have a lot of noise on the ground plane it could couple into the part and cause this double triggering you were seeing. In addition, I do not recommend that the decoupling cap be located on the bottom of the board. So since you damped down this reflection you also reduced this noise on the ground as a side effect. Now I must say that I have not seen your layout but in the past I have seen this be a problem with other customer's layouts. Thanks for the feedback and an opportunity to comment on this.

Reply
  • 0
    •  Analog Employees 
    on Oct 14, 2013 6:39 PM

    Hello BartaG,

    The internal clock will not be coming from the BCLK pin in master mode but you did expose some possible weakness in your PCB layout. Yes, proper termination of the clock lines is of huge importance and solved your issue. What was probably happening is these reflections were possibly either creating crosstalk to other clock lines but most likely it was causing a fair amount of ground bounce, or ground noise. I suggest you check the decoupling of the part very carefully. It is a subtle thing but makes a big difference. Having a .1uf cap close to the power pins is just the start. Then the connections to the power and ground planes have to be done such that the cap is between the part and the vias to the planes. We have seen problems when the via is placed between the part pin and the cap. Yes, the trace is still very short but it reduces the effectiveness of the decoupling cap. If you then have a lot of noise on the ground plane it could couple into the part and cause this double triggering you were seeing. In addition, I do not recommend that the decoupling cap be located on the bottom of the board. So since you damped down this reflection you also reduced this noise on the ground as a side effect. Now I must say that I have not seen your layout but in the past I have seen this be a problem with other customer's layouts. Thanks for the feedback and an opportunity to comment on this.

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