ADAU1961 I2S master mode

Hi,

I am trying to use the ADAU1961 as simple stereo ADC with external MCLK (12.288MHz) with 256×Fs and 48kHz sample rate.

If I set up the device to generate the BCLK and LRCLK (master mode operation), the clocks are correct but the data coming out changes

on both edges of the BCLK.

If I enable only one channel, I see data (changing on both edges of BLCK) during both level of LRCLK. (see the attached picture)

If I change the bus mode to slave, every other settings not affected, and I feed the BLCK and MCLK to the ADAU1961, the data is correct,

changing only on falling edge and the audio sounds good.

The settings:

R0 (0x4000) : 0x01

R15 (0x4015) : 0x01

R16 (0x4016) : 0x00

R17 (0x4017) : 0x00

R18 (0x4018) : 0x00

R19 (0x4019) : 0x31 (one ADC channel is enabled)

Thanks for your help.

attachments.zip
Parents
  • Hello Dave,

    Thanks for your reply I tried your sequence but with no success. The information that the register settings are correct forwards us to check the schematic and the connections again.

    We checked that every ground and power pins were connected even the expose pads.

    After we checked the I2S lines again with an active probe and found some reflection. We inserted serial

    resistors into the I2S lines and it corrected the I2S bus.

    So it seems that in master mode the internal clock for the serial digital interface also comes from the BCLK

    pin and the reflection could cause this "funny" operation.

    We use hi-speed hirose connectors between the boards and the I2S is connected to an FPGA (Lattice ECP2).

    Once again thanks for your help, I hope this thread can help others if they get the same error.

Reply
  • Hello Dave,

    Thanks for your reply I tried your sequence but with no success. The information that the register settings are correct forwards us to check the schematic and the connections again.

    We checked that every ground and power pins were connected even the expose pads.

    After we checked the I2S lines again with an active probe and found some reflection. We inserted serial

    resistors into the I2S lines and it corrected the I2S bus.

    So it seems that in master mode the internal clock for the serial digital interface also comes from the BCLK

    pin and the reflection could cause this "funny" operation.

    We use hi-speed hirose connectors between the boards and the I2S is connected to an FPGA (Lattice ECP2).

    Once again thanks for your help, I hope this thread can help others if they get the same error.

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