ADAU1961 I2S master mode


I am trying to use the ADAU1961 as simple stereo ADC with external MCLK (12.288MHz) with 256×Fs and 48kHz sample rate.

If I set up the device to generate the BCLK and LRCLK (master mode operation), the clocks are correct but the data coming out changes

on both edges of the BCLK.

If I enable only one channel, I see data (changing on both edges of BLCK) during both level of LRCLK. (see the attached picture)

If I change the bus mode to slave, every other settings not affected, and I feed the BLCK and MCLK to the ADAU1961, the data is correct,

changing only on falling edge and the audio sounds good.

The settings:

R0 (0x4000) : 0x01

R15 (0x4015) : 0x01

R16 (0x4016) : 0x00

R17 (0x4017) : 0x00

R18 (0x4018) : 0x00

R19 (0x4019) : 0x31 (one ADC channel is enabled)

Thanks for your help.
  • 0
    •  Analog Employees 
    on Oct 8, 2013 6:56 PM

    Hello BartaG

    I have setup an evaluation board in the lab and programmed it using the register settings you shown and cannot replicate the problem. I tried several things to see if I could create the same behavior you are seeing but I cannot. You do not mention how you are programming the part. I suggest you use SigmaStudio to set up the part to function the way you like then copy the register writes you see in the output window into the sequencer. Then save it as a file. You can then test the initialization commands using the sequencer before you code it into your DSP or Microcontroller. Do keep in mind that the part operates on so little power that even just an MCLK signal on its input is enough to keep the part on and not perform a full reset at power down.

    Another reason to use SigmaStudio is because there can be some registers that need to be written to that SigmaStudio will automatically do. I will attach the initialization routine that I setup with your parameters and a few other register writes. I have tested this using the evaluation board and verified that it does work. You can import this routine into the SigmaStudio sequencer. I will also attach the scope plots that I captured. Note, the evaluation board was driving the long capacitive cables to feed the I2S signals to the Audio Precision so our waveforms do not look as good as yours but you can still see that the transitions are in the correct place albeit a little delayed.

    Let us know your results so we can help narrow down your problem. If the problem persists then send a full register dump using SigmaStudio and schematics so we can better understand your application. You can send those in a private message.


    Dave T
  • Hello Dave,

    Thanks for your reply I tried your sequence but with no success. The information that the register settings are correct forwards us to check the schematic and the connections again.

    We checked that every ground and power pins were connected even the expose pads.

    After we checked the I2S lines again with an active probe and found some reflection. We inserted serial

    resistors into the I2S lines and it corrected the I2S bus.

    So it seems that in master mode the internal clock for the serial digital interface also comes from the BCLK

    pin and the reflection could cause this "funny" operation.

    We use hi-speed hirose connectors between the boards and the I2S is connected to an FPGA (Lattice ECP2).

    Once again thanks for your help, I hope this thread can help others if they get the same error.

  • 0
    •  Analog Employees 
    on Oct 14, 2013 6:39 PM

    Hello BartaG,

    The internal clock will not be coming from the BCLK pin in master mode but you did expose some possible weakness in your PCB layout. Yes, proper termination of the clock lines is of huge importance and solved your issue. What was probably happening is these reflections were possibly either creating crosstalk to other clock lines but most likely it was causing a fair amount of ground bounce, or ground noise. I suggest you check the decoupling of the part very carefully. It is a subtle thing but makes a big difference. Having a .1uf cap close to the power pins is just the start. Then the connections to the power and ground planes have to be done such that the cap is between the part and the vias to the planes. We have seen problems when the via is placed between the part pin and the cap. Yes, the trace is still very short but it reduces the effectiveness of the decoupling cap. If you then have a lot of noise on the ground plane it could couple into the part and cause this double triggering you were seeing. In addition, I do not recommend that the decoupling cap be located on the bottom of the board. So since you damped down this reflection you also reduced this noise on the ground as a side effect. Now I must say that I have not seen your layout but in the past I have seen this be a problem with other customer's layouts. Thanks for the feedback and an opportunity to comment on this.