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AD1938 Clock

hi

I am design broadcasting equipment and am using the ad1938 for the audio of the system

i have an external clock (12.288Mhz crystal) connected to the MCLKI  but i would like to just use that for the ADC  and use the BCLK from another device for the DAC .

i tried this is standalone mode and the ADC and DAC were not in sync, and now am using a microcontroller and i still can seem to the the system with with the different clocks

could you please advice me on if it can be done in standalone mode or how should i configur the registers ?

thanks

  • Hello Andrews,

    I need to know a bit more about the clocking.

    What are you using for MCLK?

    Are you sending MCLK to all the parts that require MCLK?

    Is this "other device" using this same MCLK?

    Thanks,

    Dave T

  • I'm using a 12.288Mhz crystal Oscillator

     

    The system is bi-directional ,I  am using the same product to send the audio

    So I am sending from the ADC of product1 to the DAC of product2

     

    I want too use the MCLK from the oscillator for just the ADC but then use the LRCLK for the DAC  so that the clock of the DAC in product 2 can be the same as the ADC of product 1

     

     

    I hope that's enough information for you to help me

     

    Thanks

    Andrews

  • Hi Dave ,

    i managed to get PLL input to lock in DLRCLK by setting  PLL and clock register 0 bit 5 to 1, therefor the DAC works as required .


    The problem i'm having now is PLL and clock register 1 , I cant seem to set bit 1 of that register to set to 1. In fact i cant seem to get that register to work at all,  its like that register is not responding to our code . i changed the oscillator to 24.576Mhz and still not working.

    please advice me if am missing anything

    Thanks

    Andrews

  • I'm using a 12.288Mhz crystal Oscillator

     

    The system is bi-directional ,I  am using the same product to send the audio

    So I am sending from the ADC of product1 to the DAC of product2

    I want too use the MCLK from the oscillator for just the ADC but then use the LRCLK for the DAC  so that the clock of the DAC in product 2 can be the same as the ADC of product 1

    I hope that's enough information for you to help me

    Thanks

    Andrews

  • Hello Andrews,

    In reading your description of the problem of the registers being unresponsive, I think you may be accidentally placing the part into Standalone mode. In standalone mode many of the registers are shadow registers and are bypassed so that is the behavior you will see. Have a look at Table 11 in the datasheet. If CIN, CCLK and CLATCH are all low for a period of time then the part will go into Standalone mode. With a 24.576 MHz clock on the MCLKI pin then the amount of time is 2.67 ms. Double that if it were a 12.288 MHz clock. This is easily avoided since SPI messages are far shorter in duration than 2.67ms. Where this has been a problem is when the system controller may have the SPI port on a lower priority, drops the CLATCH line low then gets interrupted before the start of the message for more than 2.67ms. Then the CCLK, CIN and CLATCH are all low for too long. Another possible source for this problem is at startup when in reset. This is best handled by placing a pull-up on the CLATCH line as recommended in the datasheet. Another strategy is to keep the CCLK line high at the end of the message and only drop it just before the start of the message.

    The only way to get it out of STANDALONE mode is to reset the part.

    I think otherwise, you are close to getting this working as you desire.

    Thanks,

    Dave T


  • Thanks for the help so far.

    We now seem to have access to all the registers, and can set the AD1938 up as we want, but have found another issue. We want the ADC to run directly from the local MCLKI/XI pin running (now) at 512xFs. The DAC should use the PLL locked to the incoming DLRCLK. Incidentally the ADC output is then sent to the DAC in another (identical) unit over fibre, which also sends back return audio over another fibre.

    The DAC works fine with the PLL locked to the DLRCLK. It appears that the ADC also works fine from the MCLKI/XI input, until we disconnect the DLRCLK input to the DAC. There is then no output from the ADC. The PLL obviously loses lock, but it appears that this also stops the ADC working from MCLKI/XI. Why might this be?

    I see a note in the description of PLL and Control Register 0 where you define the MCLKI/XI pin functionality (PLL active), master clock rate setting. What is the meaning of the 'PLL active'? Why is it mentioned? Does it mean that the MCLK/XI pin direct to the ADC does not function if the PLL is inactive or unlocked?

    Thanks.

    Andrews


  • Hello Andrews,

    Unfortunately there is no way to disable the logic that mutes both the ADCs and the DACs when the PLL is unlocked. I agree that this should not be the case but it is.

    Certainly one way to get around this it to split up the functions onto two parts. The AD1974 for the ADCs and the AD1934 for the DACs. The benefit of this solution is that there are now two PLLs so each part can operate with only using LRCLK or with a 12.288 MHz MCLK. But, it is two parts instead of one and its associated decoupling and board space.

    Thanks,

    Dave T

  • Hi Dave,

    thanks for getting back at me

    i understand the mute part , a bit of a shame .

    Could you please advise me on how to run the ad1938 of a direct clock  from PLL and Clock control register 1 ( i'm using a 24.576 Mhz crystal ) , i try setting the register 1 to b03 but i get no response , am not sure if am missing something in the schematics

    And if I pull COUT to a high does that affect it any how ??

    btw, I've been trying to call your office and its keeps going voicemail

    thanks

    Andrews

  • Hi Dave ,

    i just noticed a reply you gave in Re: AD1937 evaluation board :

    " This is setup in the "PLL and Clock Control 1 Register". So in my example, you could have the  DAC clock source, bit-0 = 1, so the DAC will get its MCLK from the MCLKI pin and then set the ADC to take its MCLK from the PLL clock, bit1 = 0. Then in the "PLL and Clock Control 0 Register" you would set the PLL input to be ALRCLK, bits 6:5 = 0b10. This will take the LRCLK coming in on the ALRCLK pin and use that to drive the PLL. Then they can both be set to slave from incoming clocks for BCLK and LRCLK and do not have to be synchronous."

    This is exactly what we want to achieve, which LP filter do we use if we want to use a direct MCLK for either the ADC or DAC. our main focus is to drive them from just the direct clock.

    And if I pull COUT to a high does that affect it any how ??

    please advice on hardware components that  need to need to be configured on the  schematics in order to achieve that assuming that the registers are set as above.

    we have bought the eval board and will be experimenting on there till we achieve our objectives.

    Thanks very much

    Andrews

  • Hi Andrews,

    I am following up to make sure that you were able to get the AD1938 working the way you want, in your system.

    Best regards,

    Coleman