AD1853 introduces spurs when given a DC offset?

Looking at the AD1952, I notice that there is a master reset timing requirement, but I don't see the same in the AD1853 data sheet.  Is the 64 clock cycle reset timing a concern on the AD1853?

Hello Ryan,

It would be good to know what sampling rate you are running at, but basically you are seeing idle tones. One of the methods for eliminating idle tones is to add a DC offset which will push the tones up out of the audio band. This is why you see it shift higher the more DC you add. The nature of idle tones will change with the input data so that behavior is to be expected.

Adding noise is another way to prevent idle tones but this will obviously reduce your SNR of the system. Adding a DC offset will reduce your headroom a little but it is often not an issue depending on the application.

You mentioned the "full 20 kHz" signal. So am I to assume you are running at 44.1 kHz? Then adding some DC or noise to "push" the idle tones over 40 kHz will make it easy to filter out with a simple RC filter on the output.

Thanks,

Dave T

Thanks, Dave,

Some observations:

- we observed the tones at 192 KHz as well at 96KHz; in our applications we use varied fSAMP values, such as 100KHz,  65KHz, 50KHz, 25KHz etc.

- we generate  signals with frequencies up to about 0.4 fSAMP; I could not find a number for fSAMP Min for 1853 or 1955;

- indeed, varying  DC in SDATA,  no AC, the tones move up and down and at some point they get out of picture (0.4 fSAMP); then, when AC signal added, for some specific range of amplitude (ex: fSAMP:100KHz, 3KHz,  -20dbFS), the tones come back as a string of products (-85dB), moving up and down in frequency (and amplitude)  with the signal frequency and amplitude.

Hello Ryan,

I have found in my testing of DACs that when I add DC the idle tones will move up out of band. But, then when I input a signal with the same peak voltage as the DC the tones will come back. However, these were very low level signals not -20 dBFS. At that level the signal should be enough to prevent the tones from appearing. The tones come in when the sigma-delta modulator has nothing to process but noise.

So I am wondering if there is something else going on. Are you setting the chip mode to a rate that is close to the allowable MCLK frequencies when you are trying all these different sample rates? You could be in a situation where the internal filters are not working properly at the rate that you are running the part at.

For instance, if you want to run at 100 kHz FS, then you will need to set the part to the INT4x mode and then feed it with an MCLK of 128xFS so that would be 12.80 MHz.

The datasheet does not specify what the min and max sampling frequencies. It only lists a few rates and 32 kHz is the minimum rate it shows. So running at 25 kHz will probably work but you may start seeing filter issues.

So what have you found since you posted this question?

Thanks,

Dave T