# SSM2604 SR setting

Hi,

We would like to use SSM2604 in the following conditions.
Is it possible?

Conditions:
・MCLK                   : 4.266666.....MHz  (256fs)
・BCLK                    : 1.066666.....MHz  (64fs=MCLK/4)
・RECLRC/ PBLRC : 16.66........kHz  (1fs=MCLK/256)
・Data-word length:16-bit
・Slave mode

If it is possible, what is the setting of SR[3:0]?

Because there are 2 options in the Table 26 of the datasheet as follows.

1)In case of MCLK=12.288MHz, BCLK=MCLK/4 and fs=48kHz,
SR[3:0]=0000
2)In case of MCLK=11.2896MHz, BCLK=MCLK/4 and fs=44.1kHz,
SR[3:0]=1000

Best regards,
Nikkee

• Hi,

According to the datasheet,
the frequency Range is from 8.0MHz(Min) to 13.8MHz(Max) in the CORE CLOCK TOLERANCE
and the internal core reference clock of the SSM2604 can be set to either MCLK or MCLK divided by 2.
So we understand that the master clock frequency should be more than 8Mhz.
Is that right?

Best regards,
Nikkee

• Hi,

According to the limitation of the core clock frequency range,
We would like to set SSM2604 as follows and know the value of SR[3:0] and BCLK frequency.

MCLK:25.6 MHz
Core clock：12.8 MHz (CLKDIV2 = 1) (768 fs)
RECLRC/ PBLRC：16.666… kHz (fs)
Normal mode
16-bit word
Slave mode

We think SR[3:0]= and BCLK=Core clock/4(3.2 MHz).
Are those right?

Best regards,
Nikkee

• Hi,

In case of previous post conditions,
according to the following limitation we think BCLK/12(1.06666..MHz) is possible.
Is it right?

BCLK in slave mode ＞ Sampling Rate × Word Length × 2

Best regards,
Nikkee

• Hello Nishimiya,

Ok, let me see if I got this right. I will walk through the settings and calculate the frequencies.

If you feed the part 25.6 MHz for the clock input, then set the CLKDIV2=1 to divide this clock by 2 so this will give you an internal MCLK frequency of  12.8 Mhz.

So now looking at the table 26 in the datasheet, the MCLK frequency used in the rest of the calculations will be 12.8 MHz. The SR[3:0] register will set the dividers to obtain the LRCLK. You quoted the value of  which is dividing the MCLK by 768. So 12.8 MHz / 768 = 16.7 kHz FS.

So then moving on to BCLK rates. This part does behave a little differently from our more current line of parts. This part you only need to tell it how many bits the data is. So when you are in slave mode with a 50/50% duty cycle LRCLK then this part is set in what the datasheet calls "Audio Mode" then the BCLK frequency needs to be high enough to clock out all the bits. I am also assuming left justified. So if you have 16 bits of data then the formula is BCLK >= 16.666 kHz x 16 x 2 = 533.312 kHz BCLK rate is the minimum.

So if you feed it exactly 533.312 kHz then:

What the part will do is start clocking out the left channel data at the high to low transition of the LRCLK. it will clock out exactly 16 bits then the LRCLK will go high and so it will start clocking out the right channel 16 bits. Since 533.312 kHz / 16.666 kHz is exactly 32, there will be 32 BCLK transitions during one sample period. This means that all the data will clock out. If the BCLK frequency were lower then there would be fewer transitions than 32 so not all the bits would transfer out before the next LRCLK High to Low transition. That transition resets everything and starts over.

So if the BCLK frequency is higher than 533.312 kHz then there will be padded bits transferred. So LRCLK high to low starts the transfer of the 16 left channel bits. On the 17th BCLK transition the LRCLK is still low so nothing is there to transfer. It will be a high or low, I am not sure. But it is just padded data. Then when the LRCLK goes high the part will start transmitting the right channel 16 bits until they are completed then it will transmit padded empty data until the next frame.

This means that you can clock it out faster but the DSP will need to know how many bits to ignore after the data and it needs to be the same way every time. In other words, referenced to the MCLK with a known number of transitions per sample period.

When this part is set in pulse mode for the LRCLK. This datasheet calls it DSP/PCM Mode. Then the part will see the pulse and start putting out the data. If it is 16 bit word size then it will put out 16 left channel bits immediately followed by 16 right channel bits and then after that if there are more BCLK transitions it will just send out padded null data until the next pulse.

This is why the BCLK specification is >= Greater than or Equal to the formula.

So your question of the BCLK frequency of MCLK/12 = 1.066... MHz is possible. So you will be clocking out at twice the minimum rate so for 32 bits of data you will be clocking out 64 bits with 32 of them being padded bits to be ignored.

Let me know if you have more questions.

Thanks,

Dave T

• Hi Dave,