Clock AD1937

Hi all


I'm doing a project using that AD 1397 connected to an FPGA. I'm a bit confused about the clock setup of the device. my strategy what's to let the ADC generate clock signals from the ABCLK and ALRCLK pins to the FPGA. I am using an external crystal connected to the MCLKXI and MCLKXO (12.288 MHz) pins and i'm not using standalone mode.


My problem it's that I'm not getting any clock signal out on the ABCLK or ALRCLK pin when measuring with my oscilloscope. In the configuration that I have made via I2C is the ADC and DAC active in PLL and clock control 0 register bit 7 (0x01) and in the ADC control 2 register is the ADC set to be master in bit 3 and 6, and ABCLK it set to be internally generated (0x13) but still no clock signal on the two pins!


Is it even possible to configure the device in this way or have i misunderstood the concept of the device functionality?


I hope you can help me sort out this issue.


Kindly regards

André

  • 0
    •  Analog Employees 
    on Apr 2, 2015 6:25 PM

    Hello Andre,

    So far what you have told me it looks like you are setting the part correctly.
    Can you send me all the register settings you are using? There are not too many registers in this part. I guess all you really need to send to me is any registers you are changing after power up.

    Thanks,

    Dave T

  • Hi Dave.

    first of all thank you for the very fast reply (7 minutes = impressive)

    Here is the register settings the i give the device after start up:

    0. PLL and Clock Control 0 register --> (0x01) Modified by me

    1. PLL and Clock Control 1 register --> (0x08) Default.

    2. DAC Control 0 --> (0x00) Default

    3. DAC Control 1 --> (0x00) Default

    4. DAC Control 2 --> (0x00) Default

    5. DAC individual channel mute --> (0x00) Default

    6. DAC1L volume control --> (0x00) Default

    7. DAC1R volume control --> (0x00) Default

    8. DAC2L volume control --> (0x00) Default

    9. DAC1R volume control --> (0x00) Default

    10. DAC3L volume control --> (0x00) Default

    11. DAC1R volume control --> (0x00) Default

    12. DAC4L volume control --> (0x00) Default

    13. DAC1R volume control --> (0x00) Default

    14. ADC Control 0 --> (0x00) Default

    15. ADC control 1 --> (0x00) Default

    16. ADC Control 2 --> (0x13) Modified by me

    I´m also going to provide you with a part of the circuit diagram where the crystal is pressend, because i´m a bit in doubt about the configuration, should it be connected to both MCLKXI and MCLKXO like I have done or will this cause problems?

    Thanks again!

    André

  • 0
    •  Analog Employees 
    on Apr 2, 2015 10:26 PM

    Thanks Andre for the info,

    Before I get to the register settings I just want to mention that you need the loop filter components stuffed on the LF pin. You need the values specified for MCLK input. The right hand drawing in Figure 32 in the datasheet. I think you may know this and just did not include it in the schematic you shared. Without these components the PLL will not function and you will have no clocks.

    Regarding the crystal. You have to hook it up the way you did using the MCLK/XI and MCLK/XO. So you are OK there.

    The next thing to mention is a small detail about the datasheet. When you look at the tables for the register settings, the first value listed is the default value. This ends up being all zeros for the registers. That was a cool thing the designers did.

    So looking at your settings...

    0. PLL and Clock Control 0 register --> (0x01) Modified by me

    This needs to be 0x80, you need to have the XTAL enabled and set the ADC and DAC enable bit, bit7. Setting bit 0 to a "1" will power down the part.

    1. PLL and Clock Control 1 register --> (0x08) Default.

    I think of the default on this to be 0x00 but it is academic since bit 3 is a read only PLL locked bit. Reading this will give you a 0x08 if it is locked. So you are fine with this register.

    2. DAC Control 0 --> (0x00) Default

    3. DAC Control 1 --> (0x00) Default

    4. DAC Control 2 --> (0x00) Default

    5. DAC individual channel mute --> (0x00) Default

    6. DAC1L volume control --> (0x00) Default

    7. DAC1R volume control --> (0x00) Default

    8. DAC2L volume control --> (0x00) Default

    9. DAC1R volume control --> (0x00) Default

    10. DAC3L volume control --> (0x00) Default

    11. DAC1R volume control --> (0x00) Default

    12. DAC4L volume control --> (0x00) Default

    13. DAC1R volume control --> (0x00) Default

    All these DAC registers look good to me.

    14. ADC Control 0 --> (0x00) Default

    You may want to turn on bit 1 to enable the HPF. It is a good idea, it removes any DC offsets present on the converter. So that would be 0x02.

    15. ADC control 1 --> (0x00) Default

    Good, no problem here.

    16. ADC Control 2 --> (0x13) Modified by me

    Here is where your problem lies. First you are set to slave so that is why you do not see any clocks.

    Bit 6 needs to be high to be in master mode. Bit 7 can stay at 0. It is really no difference because in master mode the clocks are forced to be internally generated.

    Bit 3 needs to be a 1 to have the LRCLK to be a master.

    Now as far as the format goes. So far all your settings have been for "standard" I2S. So I think you will want the LRCLK to have a 50/50 duty cycle. This all depends on how you want it and how your DSP wants to see it. There is no wrong here unless other parts are expecting it differently.

    So set ADC Control 2 --> 0x48

    I am wondering if you were looking at the bitfield backwards? This datasheet was written before we started using the pictures of the bitfields. So bit 7 is the MSB and bit 0 is the LSB. I have trouble looking at it in table form as well, I have to think about it for a second.

    Give this a go...

    Dave T

  • Hi dave.

    IT WORKS !!

    Thank you so much.

    You were right about bit order, I had reversed the order.

    I apologize for the newbie error.

    Thank again

    André

  • 0
    •  Analog Employees 
    on Apr 4, 2015 5:09 PM

    Hello Andre,

    Glad your up and running. The error you did is easy to do. Shortly after we published this datasheet we started putting in pictures of the bitfields and that helps so much. Let me know if you have any further questions.

    Dave T