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ADAV803 SRC clock question

Table 2 on page 4 of the ADAV803 datasheet lists SRS MCLK Min = 138 x Fsmax but the text on page 21 states "The SRC master clock is expected to be equal to 256 times the output sample rate."   These appear to be conflicting statements..  Please help me understand.

  • Hello Rob,

    I had this same question come up about a month ago and I looked into it. I wish I had a more definitive answer but I do not know for certain. This part was designed long ago and the design team has been split up long ago. There are some things I do know. The basic ASRC design was copied from the design that Bob Adams did on the AD1896. That part does not have this constraint but then it is just a stand alone ASRC. So many parts of the 1896 datasheet appear to be copied into this datasheet which makes sense. The best I could figure is that since this SRC is part of a larger system in this part that there must be a constraint on the output rate that the rest of the system has to contend with. Note that the output of the SRC can only go to internal destinations so I am fairly certain this is the reason for the constraint.

    I hope this helps,

    Dave T