ADAU1442 and ADAU1966 sample drops

Hi,

We have a board with one ADAU1442 and one ADAU1966 in TDM16 mode. As soon as we upload a SigmaStudio file with some processing, one output drops samples (probably almost output 1, 2, 3 or 4). You can easily see what goes wrong when we insert a sine generator of 4 kHz on channel 2 in this case. I've included the SigmaStudio file for reference. Any ideas?

20151006DSP_V7_Fout.dspproj.zip
  • Hello Dave,

    Thanks for your reply!

    The 4 inputs come from an AL1402 ADAT receiver. This is a master and provides BCLK, LRCK and 4 x IIS to the DSP BCLK0, LRCLK0 and SDATA_IN 0, 1, 2 and 3. I use the sample rate converter to convert this 8 channels of data to the DSP rate. Is there a better way to do this?

    The sample drop problem also occurs when I'm running an internal sine wave generator. The 1966 is configured in stand alone mode. I've included two pictures one with the schematic of the configuration of the DAC and one with my PCB layout. As you see the data and clock lines are quick and dirty modifications with wires. Since you say that PCB layout is critical, this might be the cause... It might be wise to first change this in my next revision board design first!

    I'm measuring the analogue signal at the output of a 13 dB gain opamp stage with filtering.

    Your comments are highly appreciated!

    Kind regards,

    Stefan

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    •  Analog Employees 
    on Oct 6, 2015 5:44 PM

    Hello Stefan,

    One thing I noticed in the project was that you are setting four of the serial input ports to slave to clock domain 0 but you have the serial input port 0 set to slave. So you are slaving to itself with the clock source not defined. So change the serial input 0 to be a master from either the 48K/96K/192K DSP clocks. I don't expect this to fix the problem but it might.

    So you can still have the other serial inputs slave to clock domain 0 but I think they all should be set to master from the internal clocks since they all have the clock outputs turned on. The setting to slave from another clock domain is handy when you are operating as a slave on one port. So you only have to connect one set of clocks to one port and then have all the other serial input ports slave to that clock domain. It saves you from having to route LRCLK and BCLK for each serial port input. But in your case where they are operating as master there is no need to have them slave from each other, just have them use the same internal DSP clock.

    Now back to this issue:

    I need to know a lot more about what is going on in your system. This could be an I2S transmission issue. TDM16 can be challenging to connect on a PCB so having a schematic would be very helpful. Looking at your PCB layout would also be handy. I also need to know the register settings on the 1966.

    I also am wondering what the input level is on the scope plot you showed me and what the output level was. In addition, what is connected to the ADAU1966 outputs?

    Another side note, you can control the ADAU1966 using SigmaStudio in the same project with the 1442. 

    Dave T

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    •  Analog Employees 
    on Oct 15, 2015 6:36 PM

    Hello Stefan,

    Sorry for the delay. I have been swamped with other urgent matters.

    Yes, these jumper wires may very well be the cause. TDM16 is rather high in frequency and as such is sensitive to poor signal integrity issues like reflections and impedance changes. I have had issues when working with evaluation boards and trying to use TDM16 that is jumping from one board to another.

    Your jumpers are quite short so that helps. You may want to try to run a ground jumper wire along with each clock or data line. Either run them touching each other or twist them together. This may help.

    On the edge of your schematic I see either jumpers or ferrite beads on the data lines. This would not be a good place to use a ferrite bead. In addition, you should have some sort of termination. I like using an RC to ground but they are more parts and a little tougher to select the correct values. At least you should use a series terminating resistor. The value should be selected from an analysis of the circuit that includes the PCB parasitic information. Normally this can result in values between 10-50 ohms and could be up to 75 ohms.

    One other thing is that you should treat the clock lines the same as the data lines since the edges need to be aligned and if the termination is different it will skew the edges a little and cause an issue.

    I would be glad to look at your design in more detail and your PCB layout if you like.

    Thanks,

    Dave T


  • Hello Dave,

    Thanks for your reply. Since I've plenty unused output pins on the DSP, I now use 2 x TDM8 instead of 1 x TDM16. I'll have to do some extensive testing but this looks promising!

    I'm finishing a new revision of this board with all modifications implemented. I would be very glad if you could review that version, but my client doesn't allow me to post schematic and board designs on the web. Can I send it to you directly?

    Kind regards,

    Stefan

  • 0
    •  Analog Employees 
    on Oct 22, 2015 5:38 PM

    Hello Stefan,

    I sent an email to you.

    Thanks,

    Dave T