AD1896
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The AD1896 is a sample rate converter; it is second generation and 24-bit, high-performance, single-chip, and asynchronous. Based upon Analog Devices experience...
Datasheet
AD1896 on Analog.com
Hello,
I´m currently developing an audio DAC device with an AD1896 ASRC to reduce bitrate abd jitter.
The input data (SCLK_IN, LRCLK_IN, SDATA_IN) comes from a CS8416 SPDIF digital reciever and looks like correct. The parameters of input data are given below:
- SCLK_IN = 2.8224 MHz,
- LRCLK_IN = 44.1 kHz,
- SDATA_IN = I2S, 24 bit.
The AD1896 is configured as show below:
- MMODE[2:0] = 000 - both serial ports are in slave mode;
- SMODE_IN[2:0] = 001 - input port mode = I2S;
- SMODE_OUT[1:0] = 01 - output port mode = I2S;
- WLNGTH_OUT[1:0] = 11 - output port bitrate = 16bit.
The AD1896 is clocked by 22.5792 MHz quartz oscillator. The SCLK_OUT and LRCLK_OUT are receiving from FPGA and looks like correct, too: SCLK_OUT = 2.8224 MHz, LRCLK_OUT = 44.1 kHz.
So, I expect to receive a valide data on SDATA_OUT pin, but it isn't.
I can send good I2S,24bit data on SDATA_IN pin, or I deassert SDATA_IN to GND - it does not matter: the data on SDATA_OUT pin look like identically bad.
So, can somebody help me to find out why the AD1896 isn`t working?
Thank you in advance!
P.S.: screen from logical analizer is below.

Hello Stanyslav,
In reading your question I do not see an obvious error on your part. It looks like you have the part setup correctly. If you could try two things.
1) Try to convert to a different rate like 48kHz. Or 88.1kHz, Whatever your FPGA can easily do. See if you have a different result.
2) Capture some scope plots done with a scope probe and not a logic analyzer. I have seen logic analyzers show nice squared off wave forms when the reality was very different when viewed with a scope. You will have to capture several traces at different horizontal rates. Show at least one FS period on the screen then zoom in on the start of the frame so we can see the first 10 or 20 BCLKs.
Dave T
Hello Dave,
Thank you for your answer.
I've changed this chip for the new one and it solved the problem.
Merry Christmas and happy new year!
Stanyslav Azyabin
Hello Dave,
I´m using the same configuration as Stanyslav. But: If both serial ports are in slave mode - what need is there for a quartz oscillator? I want to use the AD1896 only to reduce bit rate from incoming 16 to 24 bit to always outcoming 16 bit. But the outcoming sampling frequency should always be the incoming sampling frequency and no reclocking is needed. So can the MCLK_IN (Pin2) be left open or must it be connected to GND or what?
Thanks in advance
Stefan Wehmeier
Hello Stefan,
Sorry I missed your question until now.
This is not a good use of a sample rate converter. If you want to reduce the bit depth from 24 to 16 you simply truncate the 8 LSBs and you will have 16 bit data. No need to do any math.
The most difficult thing for an ASRC to do is to convert two sampling rates that are very close. The coefficients become really small and can suffer from truncation issues and can actually become unstable. Our design does a good job of protecting against this issues but to actually have the input and output be exactly the same is not a good idea.
The MCLKin pin must have MCLK present. this drives the internal digital engine that does the sample rate conversion.
Let me know if you have more questions.
Dave T