Can I use an ADAU1761 as a drop in replacement for an ADAU1961 with no register or setup changes

I have a currently working board fitted with an ADAU1961 CODEC. This has registers manually configured from an attached FPGA device. Having looked at the pinouts and register descriptions of this device and an ADAU1761 CODEC (which includes a DSP) it would appear that I should simply be able to fit the 1761 in place of the 1961 and it should function exactly the same. It doesn't. No audio comes from the device. The attempt here is to be able to do some DSP processing in future but at present I'm just trying to prove that the 1761 will drop in, in place of the 1961. There isn't a Sigma Studio project for the existing 1961 part and looking at the register set for both devices it would appear that the default settings for the additional registers associated with the DSP in the 1761 should be fine. Nevertheless no audio! So what, if any of the new registers need to be set to simply "bypass" the DSP and make the 1761 just behave as a 1961?

  • 0
    •  Analog Employees 
    on Dec 16, 2015 7:08 PM

    Hello Paul,

    You are correct in that these parts are the same but for the DSP. So when the DSP is there the default is to route the ADCs to the DSP and the DSP output to the DACs. In the 1961 that default is to and from the serial port. (of course). So you need to write to two registers to change the routing.

    Register 58 (0x40F2), is the Serial Input Route Control. I think setting "0001" will be what you want unless you are using TDM.

    Register 59, (ox40F3), is the Serial Output Route Control. Again, I think setting "0001" will be what you want.

    Let me know if this does not work for you.

    To use the DSP you will obviously have to use SigmaStudio to develop the DSP program.

    Thanks,

    Dave T


  • Thanks Dave,

    Yesterday we actually tried setting the registers you suggested to the values you suggested (before I read your reply) and also set Clock Enable 0 (40F9) to FF and Clock Enable 1 (40FA) to 03 since it would appear that these should also need to be set (eg BCLK and LRCLK surely need to function). Still no audio. So as it stands at the moment too many other changes are going on in the box, so I'm going to go back to square 1 and do just the registers you suggest and see what happens. Thanks again for the reply.

  • Hi Dave,

    Hopefully you've seen my previous reply.

    OK - we've tried adding the extra register configurations just for the routing that you suggested and this still doesn't work. I was a little confused at the TDM explanation in the datasheet for these settings - for example why should I choose 0001 when I'm not using TDM in the first place? Anyway just these registers doesn't work.

    To give you am idea of our setup we have 2 mono microphones going into the analogue input and out of the serial as data. We then have serial data coming in and out of the headphone monitor. The test setup is just looping digital out back to digital in. This all works with a 1961 CODEC. So test setup is fine. I've also loaded the code with the extra register settings into a board fitted with a 1961 and it simply seems to ignor the additional writes and works.

    There are also a couple of clock registers R65 and R66 and we've tried setting R65 to FF and R66 to 03 to enable all clocks. Still doesn't work.

    Any ideas most appreciated. I can send you a spreadsheet of our complete setup over a private mail link if that helps.

    Thanks again.

  • 0
    •  Analog Employees 
    on Dec 18, 2015 4:51 AM

    Hello Paul,

    Something is going on here and I am having trouble finding a flash of insight as to why...

    The evaluation board we use for the 1761 and the 1961 is the exact same PCB. It is the Eval-adau1x61 eval board. So I know they can drop in and work. So there is something we are both missing that will be so obvious once we find it.

    For the TDM setting you are talking about. Which register is this?

    So why don't you post the exact register writes you are sending out.

    The only difference should be the DSP registers. So with that in mind I just went through those registers thinking about what could stop it from working. So I have one thing to try.

    Try enabling the DSP and starting it up. (DSP Run)

    These are located in registers R61 and R62. It may be that these need to be set to clock the audio around the DSP. It is worth a try.

    The GPIO pin configuration can prevent the serial ports from working but they default to the proper values so I doubt that is the issue. R60.

    All the rest should not be a concern.

    Dave T

  • Hi Dave,

    The TDM Stuff I Find confusing is Registers 58 and 59. The datasheet gives us various choices here. The one we chose (and likewise you chose) was 0001, but the statement is that data can be "routed from the DSP or from any TDM slot" and we're not using TDM so that begs the question why choose slot 1? I've made the assumption here (as I guess you have - or of course you know more about what's going on than I do) that without using TDM 0001 means everything.

    Anyway, here are the registers we're setting in the 1961 device, all others are default:

       

    Extracted… Reg No. Description
    Addr Data
    4000 01 R0 Enable the Core Clock - bit 0
    4015 01 R15 Set Serial Port 0 to Master Mode
    4016 41 R16 4 => BPF="010" i.e. 48 Bit Clock cycles per LRCLK audio frame, 1 => Zero delay from LRCLK edge (in BCLK units)
    4017 03 R17 CONVSR = "110" - converter sampling rate set to fs/3 i.e. 16 KHz
    400A 71 R4 Gain for a left channel single-ended input from the LINP pin, input to Mixer 1 set to 6dB
    400B 08 R5 Left channel differential PGA input gain boost, input to Mixer 1 set to 0dB
    400C 71 R6 Gain for a right channel single-ended input from the RINP pin, input to Mixer 2 set to 6dB
    400D 08 R7 Right channel differential PGA input gain boost, input to Mixer 2 set to 0dB
    400E 00 R8 Left channel differential PGA input volume control set to -12 bB, muted and disabled
    400F 00 R9 Right channel differential PGA input volume control set to -12 bB, muted and disabled
    4019 33 R19 HPF on (ADC High Pass Filter), DMPOL normal (Digital Mic Polarity), ADC Enable both on
    401C 21 R22 Mutes the left DAC input to the left channel playback mixer (Mixer 3) - unmuted and enabled
    401E 21 R24 Mutes the left DAC input to the right channel playback mixer (Mixer 4) unmuted and enabled
    4022 00 R28 (mixer 7) Mixes the left and right playback mixers (Mixer 3 and Mixer 4) with common mode output - enabled
    4023 FD R29 Headphone volume control left enabled with volume set to -55 dB
    4024 FD R30 Headphone volume control right enabled with volume set to -55 dB
    WHY ?????????
    4023 FF R29 Headphone volume control left enabled with volume set to -55 dB AND unmute
    4024 FF R30 Headphone volume control right enabled with volume set to -55 dB AND unmute
    4025 00 R31 Volume -57dB muted
    4026 00 R32 Volume -57dB muted
    4027 00 R33 Volume -57dB muted
    4028 0E R34 Pop Suppression is enabled for 21.25 ms and not low power
    4029 03 R35 Power Management enabled on both right and left channels
    401A 00,10,20,30,40,50,60,70 R20 Value Selctable from 3 external hardwired connections
    401B 00,10,20,30,40,50,60,70 R21 Value Selctable from 3 external hardwired connections
    402A 61 R36 Left DAC enabled in mono mode and with inverted polarity
    4036 00 R67 Dejitter window size set to 0 clock cycles.

    And here's my understanding of the others:

       

    PLL Control 4002 00 R1 PLL Denominator MSB
    4003 FD PLL Denominator LSB
    4004 00 PLL Numerator MSB
    4005 0C PLL Numerator LSB
    4006 10 PLL Integer Setting, Clock Divider and Type
    4007 00 PLL Lock and Enable
    Digital Microphone / Jack Detection Control 4008 00 R2 Jack Detect off (default 5ms debounce time, and default polarity - high signal)
    Record Power Management 4009 00 R3 Boost Level 00 - default, ADC Bias 00 - default, Record Path Bias 00 - default
    Record Microphone Bias Control 4010 00 R10 Mic Bias Output Disabled - otherwise set to normal performance and 0.9Avdd
    ALC Control 0 4011 00 R11 ALC Set to off - otherwise -12 dB max gain and 24ms volume slew
    ALC Control 1 4012 00 R12 Hold time 2.67 ms, target -28.5 dB
    ALC Control 2 4013 00 R13 Attack time 6 ms, decay time 24 ms
    ALC Control 3 4014 00 R14 Noise Gate = Hold PGA constant at threshold -76.5 dB
    Converter Control 1 4018 00 R18 Set to First Pair
    Right Input Digital Volume 401B 00 R21 Set to 0 dB
    Playback Mixer Left (Mixer 3) Control 1 401D 00 R23 Right record mixer (Mixer 2) bypass gain set to Muted, Left record mixer (Mixer 1) bypass gain set to Muted
    Playback Mixer Right (Mixer 4) Control 1 401F 00 R25 Right record mixer (Mixer 2) bypass gain set to Muted, Left record mixer (Mixer 1) bypass gain set to Muted
    Playback L/R Mixer Left (Mixer 5) Line Output Control 4020 00 R26 Right playback mixer (Mixer 4) muted into Mixer 5, Left playback mixer (Mixer 3) muted into Mixer 5, Mixer 5 disabled
    Playback L/R Mixer Right (Mixer 6) Line Output Control 4021 00 R27 Right playback mixer (Mixer 4) muted into Mixer 6, Left playback mixer (Mixer 3) muted into Mixer 6, Mixer 6 disabled
    DAC Control 1 402B 00 R37 Left DAC digital volume attenuation set to 0dB
    DAC Control 2 402C 00 R38 Right DAC digital volume attenuation set to 0dB
    Serial Port Pad Control 402D AA R39 No pull up or pull down  resistors on ADC_SDATA, DAC_SDATA, LRCLK, BCLK
    Control Port Pad Control 0 402F AA R40 No pull up or pull down resistors on CDATA, nCLATCH, SCL/CCLK, SDA/COUT
    Control Port Pad Control 1 4030 00 R41 SDA/COUT pin drive strength set to low
    Jack Detect Pin Control 4031 08 R42 Pin drive strength set to low and no pull up or pull down on JACKDET/MICIN
    (Not Present in the ADAU1961 but present in ADAU1761)
    CRC Check Registers 40C0 00 R43
    CRC Check Registers 40C1 00 R44
    CRC Check Registers 40C2 00 R45
    CRC Check Registers 40C3 00 R46
    CRC Check Registers - LSB is CRCEN bit 40C4 00 R47 CRC Disabled by default
    GPIO Pin Control 40C6 00 R48
    GPIO Pin Control 40C7 00 R49
    GPIO Pin Control 40C8 00 R50
    GPIO Pin Control 40C9 00 R51 All GPIO default to Input without debounce
    Watchdog Registers 40D0 00 R52 Watchdog is disabled (bit 0 set to 0)
    Watchdog Registers 40D1 00 R53
    Watchdog Registers 40D2 00 R54
    Watchdog Registers 40D3 00 R55
    Watchdog Registers 40D4 00 R56
    DSP Sampling Rate Setting 40EB 01 R57 48 KHz set
    Serial Input Route Control 40F2 00 R58 Where the DACs receive the data from - 0000 implies DACs get data from DSP
    Serial Output Route Control 40F3 00 R59 Where the ADCs send serial data - 0000 implies it goes to the DSP by default
    Serial Data / GPIO Pin Configuration 40F4 00 R60 By default serial port is enabled and all GPIOs are disabled
    DSP Enable (bit 0) 40F5 00 R61 DSP is disabled by default
    DSP Run (bit 0) 40F6 00 R62 DSP off by default
    DSP Slew Modes 40F7 00 R63 All slew settings applied to CODEC and not DSP
    Serial Port Sampling Rate 40F8 00 R64 set to 48 KHz
    Clock Enable 0 40F9 00 R65 All Clocks Disabled - SLEWPD,ALCPD,DECPD,SOUTPD,INTPD,SINPD,SPPD
    Clock Enable 1 40FA 00 R66 Digital Clock Generator 0 and 1 disabled by default
    Generator 0 generates sample rates for the ADCs, DACs and DSP
    Generator 1 generates BCLK and LRCLK for serial port when in master mode
    Original 1961 CODEC has registers R1 to R42 plus register R67
    New 1761 CODEC additionally has registers R43 to R66

    Hopefully there's something obviously wrong here. (Apologies for the format - its copied from an Excel sheet).

    Cheers.

    Paul.