I have a question about tABDD on ADAU1977.
The ADAU1977 data sheet table 6 on p.8 says that the tABDD(SDATAOUTx delay from BCLK falling) is 18 ns at maximum.
The Figure 2. Serial Output Port Timing on p.9 shows tABDD in Left justified mode, I2S mode, and Right justified mode.
In my case this time, I am using 24.576MHz crystal so one BCLK would be about 40 ns.
18ns (or less) of tABDD is only for Left justified mode?
I am asking this because the tABDD on I2S mode on figure 2 is about 40 ns.
Happy Christmas eve Dave,
Thank you for your answer.
I understand that the tABDD on Figure2 in the ADAU1977 data sheet should have been drawn tABDD+1BCLK cycle.
Also, Thank you so much for giving me the very useful formula for my future design.
One more thing, could you please give me an asnwer for the other threads below?
About I2C format on ADAU1977(DAC) (especially this is in hurry)
About a register bit LR_POR on ADAU1977(ADC)
About register configuration sequence of ADAU1977(ADC)