I have some questions in AD1934 (DAC) SPI specification.
In terms of tCOE, tCOH, and tCOTS,
what the figure9 says and what the table 7 says are different.
Could you explain about this?
CCLK freqency is 4.1MHz so the 1CCLK period is 240ns.
In my understanding, tCOE in figure 9 is wrong.
tCOE should be between the CLATCH falling and COUT rising.
In the figure there are 14 data(D10-D23).
To sample one data, I need 240ns CCLK so 14 data would require 3.36us(=3360ns).
But the table 7 says that the tCOE max is just 30 ns. I do not understand.
Gennerally speaking, I guess CCLK "rising" would sample the data, not falling. Is this is this right information. I am asking this just in case.
The figure9 and the table7 are talking different thing.
This is just a reminder of this query.
I guess this is just a misprint of the data sheet.
Could you give me some answer please?
Yes, there are a lot of issues with the diagram and the specifications table not agreeing in this family of datasheets. So I will take them one at a time:
This is the time it takes for the output port to switch from a Hi-Z mode to driving the port when measured from the falling edge of the clock pulse where it is supposed to start driving out data. So it in the internal delay to turn on the drive stage. So it is a very small number.
So yes, it is shown in the diagram like it is the CIN that it is referring to but it is not. It is the COUT. The tCOD specification is talking about the same specification. I do not know why they put both because it is basically the same spec. The design team for this part has long been split up so there are few people I can ask.
Then the other head scratching thing is why they showed it on D9? When the data will drive out during the last byte of the three byte read transaction. The first byte is the chip address, the second is the register address, and the third will be the data byte either going to the part or coming from the part. So it will be D7-D0.
The other thing the datasheet does not go into is the burst reads or writes. I am pretty sure this part will do the same as our other parts in that as long as you keep clocking the part and not raising the CLATCH, it will automatically increment the address and read or write the next register without having to send the chip address or register address. It is very efficient.
This is the minimum time the COUT will hold its value but I think it is CCLK rising is what it should say. So you know that it will hold its value at least 30ns from when you should be sampling the data. Yes, you should sample the data on the rising edge. So I think the table is wrong because it says it is when the CCLK is falling which makes no sense.
It is drawn correctly in the figure and the description "COUT Tri-State" is a good description. The comments are just flat out wrong. It has nothing to do with the CCLK. It is the delay from when the CLATCH raises, to end the transmission, to when the COUT finally goes Hi-Z.
I hope this helps.
Thank you for your very detailed answer.
I fully understand about the tCOH, and the tCOTS.
Also, I understand the tCOE actually refers to the tCOD.
However, I could not understand when you said below. Could you please elaborate it for me?
Have a look at the ADAU1761 datasheet. Page 41 figure 56. There you will see the chip address and register address bytes being transmitted then the data being read out of the COUT pin during a read. This part has 16 bit register addressing so there are two bytes for the register address but how it works is going to be the same in the 1934 except it has only one byte for the register address. There you can see where the COUT data is showing up. It is D0 to D7 if you look at the entire set of instruction bytes as one large 24 bit transmission. ( it is 32 bit in the ADAU1761)
This datasheet also has a section about the burst writes. I am pretty sure it will behave the same way in the 1934. This may save you a few tenths of milliseconds.
But seriously, if you have three or four registers that are consecutive that need to be updated then sending out one chip address, one register address (the lowest one), and then three or four bytes of data. The part will stuff the first byte of data into the first register, then when it continues to see clocks it will clock in the next byte of data, increment the register address and then store the data in that register. Then if clocks continue it will increment and stuff the next byte into the third register etc... Saves you from resending the chip address and register address. A bit more efficient.
I still have a question about this SPI timing.
You have already given me answers for the tCOE, tCOH, and tCOT.
I am fine with your answer. Thank you so much.
tCOH and tCOT
I am thinking a case where the "Table 7 on the AD1934 data sheet p.6" is correct.
At the same time, I am doubting the accuracy of the figure.9 on p.13.
Even though you mentioned as below.
>This is the minimum time the COUT will hold its value but I think it is CCLK rising is what it should say.
>So I think the table is wrong because it says it is when the CCLK is falling which makes no sense.
>It is drawn correctly in the figure and the description "COUT Tri-State" is a good description.
>The comments are just flat out wrong. It has nothing to do with the CCLK.
>It is the delay from when the CLATCH raises, to end the transmission, to when the COUT finally goes Hi-Z.
If what the table7 is talking is correct, I guess the correct timing chart would look like the the figure I have drawn(see the attachment.)
I am hoping to get an early feed back on this.