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ADAU1361 Production
The ADAU1361 is a low power, stereo audio codec that supports stereo 48 kHz record and playback at 14 mW from a 1.8 V analog supply. The stereo audio ADCs...
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ADAU1361 on Analog.com

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STARTUP, INITIALIZATION, AND POWER ADAU1361

		
	
				

			

									
					    MAPS346
					
							

            
            			
				
									
											
			
			
				
			
			
			    	
			                    
                
				                on Jan 12, 2016 
				
			
			
		

		
		                    	    

        	    
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                The user asked if MCLK must be input earlier than applying power to the ADAU1361 when not using the PLL. The engineer responded that a valid MCLK must be applied after setting the proper divider value in register R0, and before enabling the core clock. This is necessary to ensure the core can use the MCLK before writing to registers above address 0x4002.
                        	    

                
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Hello.

 
Could you teach the input timing of MCLK?

 
Is it necessary to input MCLK earlier than "Apply power to the ADAU1361 "? (no using the PLL)

 
(ADAU1361 data sheet Page 24 of 80)

 
1.Apply power to the ADAU1361.

 
2.Lock the PLL to the input clock (if using the PLL).

 
3.Enable the core clock.

 
4. Load the register settings.

 
Best Regards,

 
MAPS346

			

			
									
		                             
                        

    

                                            
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    •  Analog Employees  
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                on Jan 12, 2016 9:44 PM
            
            
						
			            		
    
		
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    Hello MAPS346,
    
 
    You will need add an additional step, step 1.5 that is write to register R0 and set it for direct MCLK input and set the input clock frequency to the proper divider.
    
 
    Then you need to change step 2 to read "Apply MCLK". That is what the PLL is doing, you would apply the MCLK to the PLL then wait for it to lock. Once it locks then there is an internal MCLK available for the core to use. So then you enable the core.
    
 
    So for you, you will need to apply the power, set the proper divider value, and then apply the MCLK signal for the core to use. Then enable the core. You must have valid MCLK and have the core enabled before you attempt to write to registers above address 0x4002.
    
 
    Thanks,
    
 
    Dave T
    
			
    

		
			
	      

		
		
	
    
	
    
		
    
			
		
    
	
    
	
    
		
						
				
						
						
				
				
		
		
    
			
		
    
	
    

    

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                on Jan 13, 2016 7:51 AM
            
            
						
			            		
    
		
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    Hello. DaveThib
    
 
    Thank you for an answer.
    
 
    Best Regards,
    
 
    MAPS346
    
			
    

		
			
	      

		
		
	
    
	
    
		
    
			
		
    
	
    
	
    
		
						
						
				
						
				
				
		
		
    
			
		
    
	
    

    

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