Pulsing generated by the SSM2167

We seem to be having issues with the SSM2167 pulses can be heard on the output.

I believe the end of the question SSM2167 Gate question, seems to hint at the same issue regarding "pumping noise".


The problem seems to occur on the triggers of the noise threshold. Sometimes if the threshold is set just right, the triggers become periodic (just over 1Hz - variable depending on device), but we have found a fix where increasing Cavg to the datasheet max of 22uF at the very least prevents the periodic pulsing. However, the on - off trigger can still be heard quite clearly on the output.

 

When these problems occur we can see a very slight, but sudden DC shift of approximately 20mV at the VCA input.  The strange thing seems to be that this pulsing occurs on most devices, but not all of them.

 

We have tried filtering the input, output, and even between the buffer and VCA stages. When filtering before the VCA stage this DC offset seems to be removed or minimised but we can still hear the pulsing at the output. To note, we use ~25k as the maximum Rgate, but have tried a datasheet recommended 5k solution which has the same results. We have also increased the supply capacitance and added a 100nF cap in parallel, decreased the input decoupling capacitor to datasheet recommended values, and adjusted the loading to various levels, but have had no luck getting a consistent solution so far.

 

I've attached a basic schematic of this stage of our initial design, which I believe is fairly standard.

 

Would you happen to have any advice regarding the issue, or any ways as to minimise the noise pulse generated by the DC offset?

  • I suppose in our case the noise threshold is variable. The previous question simply has a solution for keeping the chip in the compression region, whereas we intend to transition between all regions.

    We are looking for ways to minimise the pulsing when transitioning between these regions.

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    •  Analog Employees 
    on Feb 27, 2016 12:28 AM over 5 years ago

    Hello Morten,

    Sorry for the delay in responding.

    I did look at your schematic and I do have some suggestions.

    I was wondering if you had some HF noise in your system that may be influencing the threshold but I am fairly sure that is not a problem, however, it does not hurt to ask you to look into that.

    I think you should have a 0.1uf decoupling on pin 10 in addition to the 4.7uf to keep HF out of the part. This is most likely not the issue but it is good practice.

    The potentiometer you are using for the gate control is too high of a value. You have 25K ohms as a max and the datasheet specifies a max of 5K ohms. It is interesting that the datasheet sites that the internal noise floor of the 2167 becomes an issue if you use a higher value. I think you have found the issue.

    One other thought I had is to ask if this pot is far away from the part? Is it mounted off the board where the wires could be picking up noise? Could it be picking up crosstalk from its own output? This can create an issue where some of its own signal will influence the threshold.

    One last thing to ask is now good are the power rails? If they are a little "soft" then they could slightly vary from when the signal is on and when it is gated. This can cause it to pump when you are close to the threshold.

    Dave T

  • 0
    •  Analog Employees 
    on Aug 2, 2018 3:23 PM over 2 years ago
    This question has been assumed as answered either offline via email or with a multi-part answer. This question has now been closed out. If you have an inquiry related to this topic please post a new question in the applicable product forum.

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    EZ Admin