I have some questions about ADAU1452.
When I send CLK by external crystal to ADAU1452's XTALIN/MCLK pin.
ADAU1452's power pin will produce a voltage even there is no power supplied to ADAU1452.
Once stop sending CLK to ADAU1452, this voltage will disappear.
If I remove ADAU1452, this phenomenon disappear too.
Customer afraid that it may have leakage issue for ADAU1452.
Now I'm using ADG779 to cut CLK signal between crystal and ADAU1452 before power up ADAU1452.
But I think it doesn't solve the root cause, can you kindly give me some suggestions?
Thanks very much!
What you have noticed is an issue with any low power part. I will expand on this a bit later...
When you have no power on the power pins, then the IOVDD = 0v. If you then input a clock…
There are so many different level translators available. The choice will depend on your need. Some of them have automatic sensing for direction. This seems like a good idea but I found…
When you have no power on the power pins, then the IOVDD = 0v. If you then input a clock that goes up to 3.3V then you are violating the MAX voltage that can be applied to an input pin. This is IOVDD + 0.3V.
So what will happen is that you will forward bias the ESD diodes that are meant to protect the pins from ESD. So the power from the clock signal will actually be trying to power up the part through the ESD diodes.
So back to the issue with low power parts. This DSP still draws a significant power so it is not that big of a problem but I have seen an issue with some of our really low power parts where you can power up and run the part with only clock inputs! No power applied! Obviously, this is not desired but it happens. The other thing I have seen is that I will power down an evaluation board while I still have clocks coming from the Audio Precision. My intent is to power up the part to obtain the default state of the part. But, the clocks will keep the power up just enough to hold the state of memory so the part does not reset to a default state! I have to make sure to shut off the clocks as well as the power.
If your system design requires that it operates with the DSP powered down and the MCLK will still be active, then you have to use a level shifter that uses the IOVDD power that is being fed to the DSP for the side of the level shifter that drives the DSP. This way when the IOVDD is off, to shut off the DSP, it will also shutdown the MCLK signal. When the IOVDD is turned back on then the MCLK signal to the DSP will be restored at the same time. This is true for any clock on any input pin and for GPIO pins etc. Any digital input pin.
As an industry, we will begin to see this happen more as parts move towards ultra low power.
Thanks very much for sharing your precious experience with me.
It seems it's hard to avoid it if I have operates with the DSP powered down and the MCLK is active.
I find this phenomenon also happen when external reset & SPI signal are active.
And it's highly appreciated if you can recommend me level shift which you may use before for solving this issue.
There are so many different level translators available. The choice will depend on your need. Some of them have automatic sensing for direction. This seems like a good idea but I found the drive strength to be very poor with these devices and caused issues when I used them in a design a few years ago. So I use the fixed direction or logic controlled direction parts as much as possible. The SN74AVC4T245 is an example of a level translator with logic controlled direction.
The FXLP34 is an example of a fixed direction single bit device. You need to check the details on any of these devices. See if it will work if one of the voltages is at 0v. Check for high frequency performance, check the drive strength, and probably other details that have to do with your design that I do not know about. My point is that I am not saying that these parts I mentioned are the correct solution for your application. I only mentioned them to get you heading in the right direction for finding the correct part for you.
Just look over your design and look for logic voltages that could be active when the DSP is powered off. Then either use a level translator or sometimes just a large resistor to limit the current.
Thanks very much for you suggestion and I think it's quite helpful for showing me a direction to solve this issue.