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AD1939 PLL unlocked?

wangzhichao
on Mar 16, 2016

hi,

I used the DEMO of  "21489 AD1939 I2S C Sampled-Based Talkthru", but PLL lock indicator in PLL and Clock Control 1 Register is always UNLOCKED ?  get stuck in an infinite loop, marked in red .


at the same time, SPI is ok, it can write or read from AD1939's Registers.

#define USE_48_KHZ_SAMPLE_RATE

//#define USE_96_KHZ_SAMPLE_RATE

//#define USE_192_KHZ_SAMPLE_RATE

 

 

/* Setup the SPI parameters here in a buffer first */

unsigned char ConfigParam1939 [] = {

            (AD1939_ADDR), DACMUTE, 0x00,

            (AD1939_ADDR), CLKCTRL0, DIS_ADC_DAC | INPUT256 | PLL_IN_MCLK | MCLK_OUT_OFF | PLL_PWR_DWN,

            (AD1939_ADDR), CLKCTRL1, DAC_CLK_PLL | ADC_CLK_PLL | DIS_VREF,

#ifdef USE_48_KHZ_SAMPLE_RATE

            (AD1939_ADDR), DACCTRL0, DAC_FMT_I2S | DAC_BCLK_DLY_1 | DAC_SR_48K,

#endif

#ifdef USE_96_KHZ_SAMPLE_RATE

            (AD1939_ADDR), DACCTRL0, DAC_FMT_I2S | DAC_BCLK_DLY_1 | DAC_SR_96K,

#endif

#ifdef USE_192_KHZ_SAMPLE_RATE

            (AD1939_ADDR), DACCTRL0, DAC_FMT_I2S | DAC_BCLK_DLY_1 | DAC_SR_192K,

#endif

          (AD1939_ADDR), DACCTRL1,  DAC_BCLK_SLAVE| DAC_LRCLK_SLAVE  | DAC_CHANNELS_2 | DAC_LATCH_MID, //Ddebug

            (AD1939_ADDR), DACCTRL1,  DAC_BCLK_SLAVE| DAC_LRCLK_SLAVE  | DAC_CHANNELS_2 | DAC_LATCH_MID, //Ddebug

            (AD1939_ADDR), DACCTRL2, DAC_WIDTH_24,

#ifdef USE_48_KHZ_SAMPLE_RATE 

            (AD1939_ADDR), ADCCTRL0, ADC_SR_48K,

#endif

#ifdef USE_96_KHZ_SAMPLE_RATE 

            (AD1939_ADDR), ADCCTRL0, ADC_SR_96K,

#endif

#ifdef USE_192_KHZ_SAMPLE_RATE 

            (AD1939_ADDR), ADCCTRL0, ADC_SR_192K,

#endif

            (AD1939_ADDR), ADCCTRL1, ADC_LATCH_MID | ADC_FMT_I2S | ADC_BCLK_DLY_1 | ADC_WIDTH_24, 

          (AD1939_ADDR), ADCCTRL2, ADC_BCLK_SRC_INTERNAL | ADC_BCLK_MASTER | ADC_CHANNELS_2 | ADC_LRCLK_MASTER  | ADC_LRCLK_FMT_50_50|ADC_LRCLK_POL_NORM|ADC_BCLK_POL_NORM, // NDdebug

          (AD1939_ADDR), ADCCTRL2, ADC_BCLK_SRC_INTERNAL | ADC_BCLK_MASTER | ADC_CHANNELS_2 | ADC_LRCLK_MASTER  | ADC_LRCLK_FMT_50_50|ADC_LRCLK_POL_NORM|ADC_BCLK_POL_NORM, // NDdebug       

          (AD1939_ADDR), DACVOL_L1, DACVOL_MAX,

            (AD1939_ADDR), DACVOL_R1, DACVOL_MAX,

            (AD1939_ADDR), DACVOL_L2, DACVOL_MAX,

            (AD1939_ADDR), DACVOL_R2, DACVOL_MAX,

            (AD1939_ADDR), DACVOL_L3, DACVOL_MAX,

            (AD1939_ADDR), DACVOL_R3, DACVOL_MAX,

            (AD1939_ADDR), DACVOL_L4, DACVOL_MAX,

            (AD1939_ADDR), DACVOL_R4, DACVOL_MAX,

            (AD1939_ADDR), CLKCTRL0, DIS_ADC_DAC | PLL_IN_MCLK | MCLK_OUT_OFF | INPUT256 | PLL_PWR_UP,

            (AD1939_ADDR), CLKCTRL0, ENA_ADC_DAC | PLL_IN_MCLK | MCLK_OUT_OFF | INPUT256 | PLL_PWR_UP,

            (AD1939_ADDR), DACMUTE, 0x00,

            } ;

void Init1939viaSPI()

{

    int configSize = sizeof(ConfigParam1939);

    int i,j=0 ;

    unsigned char tmpA[sizeof(ConfigParam1939) / 3];

 

    //Set up AD1939

    SetupSPI1939(AD1939_CS);

 

 

    //Write register settings

    for(i = 0; i < configSize-6; i+=3)

    {

        Configure1939Register(ConfigParam1939[i], ConfigParam1939[i+1], ConfigParam1939[i+2], AD1939_CS);

        Delay(272);

 

        //Read back register settings for debugging

        AD1938_Regs_Read[j++] = Get1939Register(ConfigParam1939[i+1], AD1939_CS);

        Delay(272);

    }

 

    // Make sure the PLL is locked before enabling the CODEC.

 

    LockTest = Get1939Register(0x1, AD1939_CS);

    while (!(LockTest & AD1938_PLL_LOCK))

    {

    LockTest = Get1939Register(CLKCTRL1, AD1939_CS);

    LockCount++;

    }

 

    for(i = configSize-6; i < configSize; i+=3)

    {

        Configure1939Register(ConfigParam1939[i], ConfigParam1939[i+1], ConfigParam1939[i+2], AD1939_CS);

        Delay(272);

 

        //Read back register settings for debugging

        AD1938_Regs_Read[j++] = Get1939Register(ConfigParam1939[i+1], AD1939_CS);

        Delay(272);

    }

    DisableSPI1939();

}

 

 

Others, I changed the Crystal Oscillator from 12.288MHz to 24MHz, the PLL is ok and locked.

  • 0
    •  Analog Employees 
    on Mar 16, 2016 1:22 PM

    Moved to correct Community

  • 0
    •  Analog Employees 
    on Mar 16, 2016 6:56 PM

    Hello Wang,

    I am the support person for the AD1939 so this is why I looked into your post.

    Since it appears you are able to read the registers then communications are working. Plus, you say you check the register and it says the PLL is locked.

    What is AD1938_PLL_Lock? Is it a define or is it a variable? It should be an 0x08.

    It appears you are waiting a long time for the PLL to lock when I look at the loop above the PLL testing code. So that is OK.

    So what do you get when you set a breakpoint after the first time LockTest is set? What is in that variable?

    Thanks,

    Dave T

  • 0 on Mar 17, 2016 6:39 AM

    Hello Dave, thank you for the answer,


    1、#define AD1938_PLL_LOCK     (0x08)

    2、LockTest = Get1939Register(CLKCTRL1, AD1939_CS);  The value of LockTest is 0x00.


    the result is " while (!( 0x00 & 0x08)) " , so it shows that PLL is UNLOCKED. the code gets stuck in an infinite loop.


    I do not know how it happened, and how to solve. Looking forward to your answer

  • 0
    •  Analog Employees 
    on Mar 17, 2016 7:42 PM

    Hello Wang,

    Thanks for the information. Since "LockTest" = 0 this means the PLL is not locked.

    So ANDing this with 0x08 will yield a "0" then !0 = 1 so it will stay in the While loop forever because the PLL does not seem to be locked.

    So let's focus on the hardware.

    You changed the crystal to a 24MHz crystal. Have you looked at it on a scope to see that there is a signal on the MCLKIN pin?

    What sampling rate do you wish to run the codec at? I think your problem is that you have the Master Clock rate setting set to 256x when it should probably be set to 512x. Way up in the beginning of the code you listed it is setting it to 256. "INPUT256". Try to set it to INPUT512".

    So putting in 24MHz and dividing it by only 256 will violate the max MCLK frequency of 13.8MHz. So it has to be set to 512.

    So I need to understand why you changed the MCLK frequency? What is your desired sampling rate? Is the crystal exactly 24MHz and not 24.576MHz?

    Dave T

  • 0 on Mar 18, 2016 7:01 AM

    Hello Dave,


    Thank you for the answer.


    Currently, I just want to initialize AD1939 by SPI based on 12.288M crystal as shown in the schematic.


    I changed  the crystal from 12.288M to 24M for test only, i won't use 24M at last.

    I hope "DAC/ADC clock source = PLL clock @ 256 fs, 384 fs, 512 fs, and 768 fs" will work  well  on 12.288M.


    Could you see if there is something wrong with my schematic diagram?