quesions about ADAU1979

hello,

during my work o ADAU1979 i have some odds and some questions about some ambiguity and less-information stuffs.

1. when i work with SPI of ADAU1979, I found that i should provide SCLK regardless of CS active. since my cortex M3 controller gives out SCLK only when CS is active, i had to bring some tricks on. anyway, this is not an issue anymore, but is this behavior what the SPI of this chip is designed?

2. i had to use AD628 just before the 1979. because i need some attennuation on audio signal. but AD628 gives out single ended output. because i don't want to use coupling capacitor, i got the vref of 1979 and through a voltage follower

and i feed this to each AD628's Vref input and 1979's each inverting inputs.with this, ADC's input common mode Vtg gap is minimal.

-2.1 on ADAU1979 datasheet, page 14, i read this clause

"In most audio applications, the dc content of the signal is removed by using a coupling capacitor. However, the ADAU1979 consists of a unique input structure that allows ac coupling of the input signals. The typical input resistance is approximately 32 kΩ from each input to AGNDx."

removing DC contents of the signal using cap coupling is the AC coupling. right? what does this mean exactly?

i understood this device is capable of dc coupling. i don't know exactly how ( for there is no explanation, no data)

but decided to trust it' is possible. i did the vref vtg follower thing though. because it is what i shoud do at least.

2-2 controlregister 'HIGH-PASS FILTER AND DC OFFSET CONTROL REGISTER AND MASTER MUTE REGISTER'

at address 0x0E, bit0 DC_CAL.

do i have to this bit on? or do i have to DC calibration from time to time? does this have impact on ADC's channel output data?

2-3 controlregister 'DIGITAL DC HIGH-PASS FILTER AND CALIBRATION REGISTER'

at address 0x1A,

if i set this byte to 0, ADC's vref output does not showing 1.5V, adc output TDM stops working (logic 1 all the time..)

what is this register for?

2-3 if i raised AD628's output by 1.5v by feeding 1979's vref value to Vref pin of AD628, and feed vref back to 1979's inverting input, this situation is identical to ac coupling using coupling cap. what happens in this case, if i set the bit DC_SUBCx to 1 and let the chip subtract DC calibration from channel converted value? I am concerned that this subtract additional 1.5V from right difference value of noninverting pin minus inverting pin.

did i do things right? since i set the bits to 0, the vref is gone and data do not come out of the chip.

what should i do?

thank you

Jeremy.

Parents
  • hello.

    i am in hardware debugging stage and doing audio signal IO channel path setups.

    i think it would be better being more specific about issue.1,  SPI.

    my controller is EFM32GG device and SPI is working as master (ADC slave) @ 4Mhz CLK

    i have worked with this chip's SPI @ well above 4Mhz between MCUs many times. so with MCU side SPI, i am quite sure that there is no pitfalls at all on MCU side.

    at first, i set the MCU's 'AUTO_CS' feature on,which controls SPI- configured synchronous port's CS# automatically when data starts or done output on MOSI pin.

    this is quite indispensable at higher rate, because MCU keeps output buffer and it is quite obscure when the data IO actually  end at the pin from programmer's point of view.

    ADC_CS is pulled up with 10Kohm resistor, software do hardware reset on power on, wait about 200mS and do dummy write 3 tiimes.

    when i put the power on, DVDD pin is active with 1.8V, but no vtg on VREF pin (logic 0) and no activity on TDMO pin.

    i checked and revised software code many time in vain.

    some uncleared matter i hit upon, in default, ADC uses I2C and trasfer to SPI mode with no coming back,

    1. then do i need to keep SCL/CCLK alive? but CS pin is dedicated, no sharing.

    2. then set CS low 3 times can / should be done with no cclk? but they said that do it with 3 dummy SPI writes..

    3. shortly, the port controller state ,when do CS low 3times,was obscure, it is neither in SPI state machine ,because is is not turned on, nor I2C bacause I2C SCL is not clock input for chip's I2C interface it is merely tristate I/O pin.

    so i decided to keep CCLK active all the time, which is no violation of SPI specification for a SPI slave device.

    i set the AUTO_CS off, use both the interrupt and non-interrupt I/O code.

    1. in ISR, keep writing dummy data on SPI output. this makes the CCLK always alive.

    2. in don-interrupt I/O code, i disable interrupt, set CS low, and do data write loop. when actual data output finishes,SET CS high, then enable interrupt.

    MCU works on 48Mhz , and SPI port is working at 4 Mhz, so there may exists some jitters on SPI CCLK when actual data write is done. which seems not to be a severe issue with 12 times working clock of MCU.

    with above, when i was done with register writing, VREF pin shows 1.5V, activities on TDM output pin,

    and the rest of the questions in original post remains..

    i admit that at the time of writing, at6 a.m. local time, i was somewhat annoyed with this obscurities and all those experiments and debugging work. and, i am not a born-english-languaged person.

    so my appology to any of the reader who might felt unneasy and annoyned.

    thank you.

    Jeremy.

Reply
  • hello.

    i am in hardware debugging stage and doing audio signal IO channel path setups.

    i think it would be better being more specific about issue.1,  SPI.

    my controller is EFM32GG device and SPI is working as master (ADC slave) @ 4Mhz CLK

    i have worked with this chip's SPI @ well above 4Mhz between MCUs many times. so with MCU side SPI, i am quite sure that there is no pitfalls at all on MCU side.

    at first, i set the MCU's 'AUTO_CS' feature on,which controls SPI- configured synchronous port's CS# automatically when data starts or done output on MOSI pin.

    this is quite indispensable at higher rate, because MCU keeps output buffer and it is quite obscure when the data IO actually  end at the pin from programmer's point of view.

    ADC_CS is pulled up with 10Kohm resistor, software do hardware reset on power on, wait about 200mS and do dummy write 3 tiimes.

    when i put the power on, DVDD pin is active with 1.8V, but no vtg on VREF pin (logic 0) and no activity on TDMO pin.

    i checked and revised software code many time in vain.

    some uncleared matter i hit upon, in default, ADC uses I2C and trasfer to SPI mode with no coming back,

    1. then do i need to keep SCL/CCLK alive? but CS pin is dedicated, no sharing.

    2. then set CS low 3 times can / should be done with no cclk? but they said that do it with 3 dummy SPI writes..

    3. shortly, the port controller state ,when do CS low 3times,was obscure, it is neither in SPI state machine ,because is is not turned on, nor I2C bacause I2C SCL is not clock input for chip's I2C interface it is merely tristate I/O pin.

    so i decided to keep CCLK active all the time, which is no violation of SPI specification for a SPI slave device.

    i set the AUTO_CS off, use both the interrupt and non-interrupt I/O code.

    1. in ISR, keep writing dummy data on SPI output. this makes the CCLK always alive.

    2. in don-interrupt I/O code, i disable interrupt, set CS low, and do data write loop. when actual data output finishes,SET CS high, then enable interrupt.

    MCU works on 48Mhz , and SPI port is working at 4 Mhz, so there may exists some jitters on SPI CCLK when actual data write is done. which seems not to be a severe issue with 12 times working clock of MCU.

    with above, when i was done with register writing, VREF pin shows 1.5V, activities on TDM output pin,

    and the rest of the questions in original post remains..

    i admit that at the time of writing, at6 a.m. local time, i was somewhat annoyed with this obscurities and all those experiments and debugging work. and, i am not a born-english-languaged person.

    so my appology to any of the reader who might felt unneasy and annoyned.

    thank you.

    Jeremy.

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