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Unexpected noise spikes on ADAU1978

I have built two identical prototype boards to evaluate the ADAU1978 4-channel ADC. The circuit is based directly on the example schematic in the ADAU1978 datasheet, and to test the noise floor all four channels are allowed to self-bias to mid-rail, and each channel has a 1K resistor between the +ve and -ve input pins.

At a sample rate of 48kSPS both boards work well, and the noise floor is close to the value expected from the datasheet. However, at higher sample rates both boards generate samples which include unexpected 'noise spikes'. The characteristics of these spikes is as follows:

* The 'spikes' consist of a sudden deviation from the mean value in one direction for one sample, immediately followed (on
the next sample) by a large swing in the opposite direction. Sometimes the third sample also shows a large deviation, in the same direction as the first one.

* The spikes occur on all four channels of each ADC, and on both boards. On some channels the 'spikes' appeared to be quite regular (although the repetition rate varies between channels, and over time), whilst on other channels the timing of the spikes appears to be random.

* At a sample rate of 192kSPS, the 'spikes' have absolute amplitudes of 2000 – 3000 peak-to-peak, typically, so the impulses are only about 75dB below the full-scale limit of the ADC. At 96kSPS the amplitude is reduced to about 85dB below full-scale, and at 48kSPS the spikes have gone completely (or are below the normal noise floor).

 

I have tried increasing the decoupling on all the supply rails, and on the reference voltage pin, and have also tried powering the ADC board from a separate battery supply to eliminate any noise on the supply rails from the processor board. Nothing that I have tried so far has any discernible effect on the spikes.

Has anyone else seen this behaviour from the ADAU197x ADCs at higher sampling rates, please? If so, did you find a way to reduce the amplitude of the 'spikes'? For my sensor application I would like to achieve 90dB of dynamic range at 192kSPS if at all possible, so it is unclear at the moment if the ADAU1978 can be used for this purpose.

  • Hello Alan,

    To understand the issue you are observing in your setup can you also specify how you configured the serial port for 96K/ 192k operation? It would be good if you could send the register settings you used for this test. Are you using the serial port as Master or Slave? Also what is the master clock for the ADAU1978?

    Is it possible to get the FFT capture of the ADC output?

    Regards

    Rajeev

  • Hi Rajeev,

     

    Thank you for responding so quickly to my question.

     

    The ADAU1978 is configured as I2S master, so it is supplying the BCLK and

    LRCLK signals. I am providing a 6.144MHz Master Clock from my CPU board

    which I believe is clean and reasonably low-jitter. (Actually the Master

    Clock is currently 6.00MHz, but I don't think that is relevant to the

    issue.)

     

    The register settings which I have been using for most of my testing at

    192kSPS are as follows:

      Reg 0x00 = 0x01

      Reg 0x01 = 0x40

      Reg 0x04 = 0x3F

      Reg 0x05 = 0x04

      Reg 0x06 = 0x01

      Reg 0x07 = 0x10

      Reg 0x08 = 0x32

      Reg 0x09 = 0xF0

      Reg 0x0A = 0xA0

      Reg 0x0B = 0xA0

      Reg 0x0C = 0xA0

      Reg 0x0D = 0xA0

      Reg 0x0E = 0x02

      Reg 0x19 = 0x00

      Reg 0x1A = 0x00

     

    (All other registers are reserved, and I do not attempt to program them.)

     

    Here is an FFT of channel 1 from a typical test run, but I'm afraid that it

    isn't terribly helpful:

    (x is multiples of clock frequency, y is dB).

     

    I hope that I have provided all the information that you need at this point?

     

    Best regards,

       Alan Rowe

  • by Reg 0x04 = 0x3F, Reg 0x05 = 0x04, Reg 0x06 = 0x01, it seems that you want to do it with 4 channels, 32 bits per slot, using 2 output pins, @ 192Khz sample rate.

    it needs 64 clocks for all 4 channels to sweep one sample packet into two output pins.

    with Reg 0x01 = 0x40 (MCS = 2'b000) in Table.9, 6.144Mhz Mclk gives only 32 clocks @ 192Khz sample rate.

    i think you should use it with 12.288 Mhz Mclk clock with MCS = 2'b001 (Reg 0x01 = 0x41)

    and when MCLK need to be 6.144Mhz, it should be 6.144Mhz with regard to predefined sample rate. of course. i think it might be that with all output register setting fixed, varying MCLK may only vary the sample rate, but who knows? at least this part is an audio ADC. (does it only mean that this part is a sigma delta ADC?) when sample rate is variyng out of audio standard, i am quite curious about the I2S receiver that receives the sampled packet from this ADC. it is another question.

    is the receiver works ok?

    and i wonder why you are driving MCLK from CPU board if you use this chip as I2S master, instead of using local crystal or oscilator.

    if you have to do multiple of 4channels using multiple of ADCs, and to aggregate all the signnals into one packet, and send it to another serial audio or serial device, (perhaps using FPGA....) you need to feed clocks from ADC receiver.because each clock and timing characteristic should be same, to prevent any bit error in FPGA.  but in that case, both MCLK and BCLK should be sent.

    Jeremy.

  • Hi Jeremy,

    Thanks for your reply - you gave me a lot to think about  :-)

    Regarding your first point, I find that the ADAU1978 generates a BCLK of 12.288MHz when I program it with the configuration values which I listed, and then provide a 6.144MHz MCLK. So the BCLK generated by the ADAU1978 (in Master mode) does not need to be <= MCLK.

    The I2S receivers which I am using for my current tests are on-chip peripherals in an STM32F4xx microcontroller. The datasheet for the MCU doesn't suggest that any specific bit-clock rates are required, and in practice I have found that they work well over a very wide range of bit-clock frequencies. I have proven that the ADAU1978 works well with this setup at 48kSPS, 96kSPS and 192kSPS, and for large signals I get exactly the output which I expect. It is only when I am trying to measure very small signals that the low-level noise spikes become intrusive.

    I am generating MCLK on the CPU board at the moment *only* for convenience while I prototype the system. On the target hardware a separate low-jitter clock generator will provide the MCLK signal.

    I will try running the ADAU1978 with a faster MCLK and see if this reduces the noise spikes - there is no problem generating a faster MCLK, I was just trying to keep it as low as possible to minimise RFI issues.

    Thanks again, and best regards,

       Alan.

  • hi Alan..

    the symptom your ADC shows somewhat resembles what is in case of receiving and sending audio packets with FPGA when there is some jitter or phase problem between BCLK and LRCLK which can easily happen one bit error of counter in state machine for any reason. (if this happens in normal audio input. and you feed this to the DAC, then you get DAC analog output which looks like that of a comparator..)

    but this seems not the case if the ADC gives out right BCLK and LRCLK..

    then, in ADC, the most probable reason for bit error is the oversampling clock respect to sampling frequency and sampling bits in sigma-delta modulator in ADC.

    is it really appropriate if we think MCLK PLL only needed to make BCLK in master mode? I am not sure of this because there is no data (not even a block diagram..) in the datasheet to judge this issue at all. and seems there is no relevant application notes. a pll usually synthesize clock. but it can be used just to reduce the jitter of a clock. (like Si5317 in slicon labs..)

    your experiment thing makes me confused now. (actually i used ADAU1979 which is same part in Converter itself.)

    because i have never doubted MCLK >= BCLK..

    two things.

    on page 19, "However, in master mode, the maximum bit clock frequency (BCLK) is 24.576 MHz. For example, for a sample rate of 192 kHz, 128 × fS is the maximum possible BCLK frequency." why? do they use separate PLL for TDM and other? of course not. I thought this highly suggets that BCLK can't be above MCLK.

    and Table 9 itself. it goes with ' "Required" Input Master Clock Frequency'..not "Required MCS values".. 

    why did they designate specific sample frequency multiplication ratio and MCLK frequency?

    if PLL synthesizes every clock in ADC, and MCS means frequency multiplication factor of sampling frequency with mclk,, , then naturally get lowest frequency and set multiplication factor for any clock according to other setting values. that's it.

    i don't really like quessing things with a device. but after all, device working. and performance is good. then everything is good.

    well I do wish you a success..

    Jeremy.