I have a problem with a project I am working on. The project consist of a ADAU1451, two ADC´s and one DAC and is configured like shown in this picture:
Both the ADC´s and the DAC have been configured to Slave mode, therefore the LRCLK and BCLK must be provided from the ADAU1451.
(I wish to have a sample rate of 48KHz)
The problem I am having, is that the LRCLK and BCLK are "wrong" in my opinion (I wish to have a sample rate of 48KHz). If I have the following selected in the SigmaStudio:
- PLL CLK SRC = Direct from MCLK
- PLL CTRL0 = 96
- PLL CTRL1 = Div by 4
- Start Pulse = base_fs (48HKz)
- All out/input data ports are set to a sample rate of fs.
The LRCLK and BCLK for the ADC´s would be 4 times too slow, I would expect to see a LRCLK of 48KHZ and a BCLK of 3.072MHz but instead I get 12KHz and 768KHz? Is this right or am I doing something wrong in the settings? If i change the PLL CLK SRC to PLL clock the LRCLK and BCLK becomes 6 times too fast - 288KHz and 18.432MHz?
The same happens to the DAC´s LRCLK and BCLK except the BCLK is two times faster - As it should be because the DAC is in TDM4 mode so there are double the data per frame.
Does anyone have a clue on what is going on here? I have attached the SigmaStudio program if it is of any help.
Thanks for helping