Daisy Chaining two AD1938 codecs - ALSA System on Chip driver

Hi there,

we are trying to extend our audio system by daisy chaining two AD1938 audio codecs. From the datasheet I got the information that both codecs are configured equally (512 fs DACs / 256 fs ADCs / single line TDM mode). So, of course, both codecs appear as one codec to the platform DAI. I think it should work, if both codecs are configured equally in series via regmap in the codec driver. For example:

static int ad193x_hw_params(...){

   ...

   regmap_update_bits(ad193x_0->regmap, AD193X_PLL_CLK_CTRL0, AD193X_PLL_INPUT_MASK, master_rate);

   regmap_update_bits(ad193x_1->regmap, AD193X_PLL_CLK_CTRL0, AD193X_PLL_INPUT_MASK, master_rate);

   ...

}

Does anybody know, how to pass two regmap configs to the driver, so that I can configure both codecs in the same way? Or any other idea how to get two daisy chained codecs working with ALSA?

Thanks!

Parents
  • 0
    •  Analog Employees 
    on Oct 17, 2016 11:39 PM

    Hello henrix,

    Basically, you do not want to run in Aux mode. This is for an auxiliary stereo DAC that will be running at a different rate. You just want two codecs to behave like one 16 channel codec correct?

    Look at table 12 in the datasheet. It shows what pins are input and which are outputs in each mode.

    I will write in responses in Red below.

    I found a way to register auxiliary devices in ASoC core. There is an extra property "aux_dev" in snd_soc_card structure for these applications. The connections of the codecs and the DSP (BeagleBone Green) are like this:

    - clock signals are connected as described in the circuit sketch

    - DAC TDM signal from DSP <-> DSDATA1 of "master" codec

    - DSDATA2 of "master" codec <-> DSDATA2 of "aux" codec  No, DSDATA2 is an output. Setup both codecs the same as TDM mode not "Aux" Mode.

    - ADC TDM signal to DSP <-> ASDATA1 of "master" codec

    - ASDATA2 of "master" codec <-> ASDATA1 of "aux" codec

    - ASDATA2 of "aux" codec <-> GND

     

    The registers settings of the codecs are both like this:

    [ 477.090537] ad193x spi32766.0: AD193X register 0: 0x5 0x5 is for 512x fs master clock input. Is that what you have? I expect you have 12.288MHz master clock. You need to have bits 2:1 = 00 for 256x fs. These calculations are based on 48kHz fs. If you setup the part to run at a different sampling rate it will adjust the dividers. 

    The first bit, bit 0, is set to 1. This powers down the part. I think you want it powered up...

    Wait, I was looking below and noticed that I think you have the bit reversed. Bit 0 is the LSB and bit 7 is the MSB.

    In that case bit 7 is a 1 and bits 6:5 is 10? So enable the ADC and DAC, and use the ALRCLK as the input to the PLL. If you do use LRCLK then you must have the proper loop filter components on the PCB. It is in the applications circuits part of the datasheet.

    so 0x5 is 0xA0  this is what you intended correct? 


    [ 477.090685] ad193x spi32766.0: AD193X register 1: 0x0
    [ 477.090815] ad193x spi32766.0: AD193X register 2: 0x40, This one does not look backwards. 

     477.090946] ad193x spi32766.0: AD193X register 3: 0x3e //0x03 for aux codec (lbclk and lrclk slave (DACs))

    I would set both up for 0x3E, Both as slaves and both in TDM mode.


    [ 477.091077] ad193x spi32766.0: AD193X register 4: 0x18, This should be 0x00.
    [ 477.091208] ad193x spi32766.0: AD193X register 5: 0x0
    [ 477.091337] ad193x spi32766.0: AD193X register 6: 0x0
    [ 477.091465] ad193x spi32766.0: AD193X register 7: 0x0
    [ 477.091594] ad193x spi32766.0: AD193X register 8: 0x0
    [ 477.091724] ad193x spi32766.0: AD193X register 9: 0x0
    [ 477.091855] ad193x spi32766.0: AD193X register 10: 0x0
    [ 477.091986] ad193x spi32766.0: AD193X register 11: 0x0
    [ 477.092115] ad193x spi32766.0: AD193X register 12: 0x0
    [ 477.092245] ad193x spi32766.0: AD193X register 13: 0x0
    [ 477.092374] ad193x spi32766.0: AD193X register 14: 0x1 Do you want the ADCs powered down? That is what 0x01 will do.
    [ 477.092503] ad193x spi32766.0: AD193X register 15: 0x23 I would keep this to 24 bits. 0x20
    [ 477.093773] ad193x spi32766.0: AD193X register 16: 0x7c //0x34 for aux codec (lbclk and lrclk slave (ADCs)) Make them both the same but one might have to be a master and one a slave. I will have to look at your clocking diagram again cannot while editing this. So do you want to be running in TDM8? 512 BCLK per frame is TDM16.

     

     When I test the DAC outputs sequentially the master codec will correctly output the test signal (sine) from audio channel 9 to channel 15, but nothing happens with the aux codec. When I swap the DAC connections like this:

    - DAC TDM signal from DSP <-> DSDATA1 of "aux" codec

    - DSDATA2 of "aux" codec <-> DSDATA2 of "master" codec Again, DSDATA2 is an output. So it will be DSDATA2 --> DSDATA1

    the sine test signal is available from channel 1 to channel 8 on "master" codec. So the hardware connections should be fine, but I don't get any output from the aux codec. Does the aux codec need a different configuration or anything else?

     

    Thanks a lot!

Reply
  • 0
    •  Analog Employees 
    on Oct 17, 2016 11:39 PM

    Hello henrix,

    Basically, you do not want to run in Aux mode. This is for an auxiliary stereo DAC that will be running at a different rate. You just want two codecs to behave like one 16 channel codec correct?

    Look at table 12 in the datasheet. It shows what pins are input and which are outputs in each mode.

    I will write in responses in Red below.

    I found a way to register auxiliary devices in ASoC core. There is an extra property "aux_dev" in snd_soc_card structure for these applications. The connections of the codecs and the DSP (BeagleBone Green) are like this:

    - clock signals are connected as described in the circuit sketch

    - DAC TDM signal from DSP <-> DSDATA1 of "master" codec

    - DSDATA2 of "master" codec <-> DSDATA2 of "aux" codec  No, DSDATA2 is an output. Setup both codecs the same as TDM mode not "Aux" Mode.

    - ADC TDM signal to DSP <-> ASDATA1 of "master" codec

    - ASDATA2 of "master" codec <-> ASDATA1 of "aux" codec

    - ASDATA2 of "aux" codec <-> GND

     

    The registers settings of the codecs are both like this:

    [ 477.090537] ad193x spi32766.0: AD193X register 0: 0x5 0x5 is for 512x fs master clock input. Is that what you have? I expect you have 12.288MHz master clock. You need to have bits 2:1 = 00 for 256x fs. These calculations are based on 48kHz fs. If you setup the part to run at a different sampling rate it will adjust the dividers. 

    The first bit, bit 0, is set to 1. This powers down the part. I think you want it powered up...

    Wait, I was looking below and noticed that I think you have the bit reversed. Bit 0 is the LSB and bit 7 is the MSB.

    In that case bit 7 is a 1 and bits 6:5 is 10? So enable the ADC and DAC, and use the ALRCLK as the input to the PLL. If you do use LRCLK then you must have the proper loop filter components on the PCB. It is in the applications circuits part of the datasheet.

    so 0x5 is 0xA0  this is what you intended correct? 


    [ 477.090685] ad193x spi32766.0: AD193X register 1: 0x0
    [ 477.090815] ad193x spi32766.0: AD193X register 2: 0x40, This one does not look backwards. 

     477.090946] ad193x spi32766.0: AD193X register 3: 0x3e //0x03 for aux codec (lbclk and lrclk slave (DACs))

    I would set both up for 0x3E, Both as slaves and both in TDM mode.


    [ 477.091077] ad193x spi32766.0: AD193X register 4: 0x18, This should be 0x00.
    [ 477.091208] ad193x spi32766.0: AD193X register 5: 0x0
    [ 477.091337] ad193x spi32766.0: AD193X register 6: 0x0
    [ 477.091465] ad193x spi32766.0: AD193X register 7: 0x0
    [ 477.091594] ad193x spi32766.0: AD193X register 8: 0x0
    [ 477.091724] ad193x spi32766.0: AD193X register 9: 0x0
    [ 477.091855] ad193x spi32766.0: AD193X register 10: 0x0
    [ 477.091986] ad193x spi32766.0: AD193X register 11: 0x0
    [ 477.092115] ad193x spi32766.0: AD193X register 12: 0x0
    [ 477.092245] ad193x spi32766.0: AD193X register 13: 0x0
    [ 477.092374] ad193x spi32766.0: AD193X register 14: 0x1 Do you want the ADCs powered down? That is what 0x01 will do.
    [ 477.092503] ad193x spi32766.0: AD193X register 15: 0x23 I would keep this to 24 bits. 0x20
    [ 477.093773] ad193x spi32766.0: AD193X register 16: 0x7c //0x34 for aux codec (lbclk and lrclk slave (ADCs)) Make them both the same but one might have to be a master and one a slave. I will have to look at your clocking diagram again cannot while editing this. So do you want to be running in TDM8? 512 BCLK per frame is TDM16.

     

     When I test the DAC outputs sequentially the master codec will correctly output the test signal (sine) from audio channel 9 to channel 15, but nothing happens with the aux codec. When I swap the DAC connections like this:

    - DAC TDM signal from DSP <-> DSDATA1 of "aux" codec

    - DSDATA2 of "aux" codec <-> DSDATA2 of "master" codec Again, DSDATA2 is an output. So it will be DSDATA2 --> DSDATA1

    the sine test signal is available from channel 1 to channel 8 on "master" codec. So the hardware connections should be fine, but I don't get any output from the aux codec. Does the aux codec need a different configuration or anything else?

     

    Thanks a lot!

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